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Searched refs:SchedWrite (Results 1 – 23 of 23) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZSchedule.td15 def NormalGr : SchedWrite;
16 def Cracked : SchedWrite;
17 def GroupAlone : SchedWrite;
18 def GroupAlone2 : SchedWrite;
19 def GroupAlone3 : SchedWrite;
20 def BeginGroup : SchedWrite;
21 def EndGroup : SchedWrite;
24 def LSULatency : SchedWrite;
40 def "FXa"#Num : SchedWrite;
41 def "FXb"#Num : SchedWrite;
[all …]
H A DSystemZScheduleZ13.td73 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
97 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z13_FXaUnit]>;
98 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z13_FXbUnit]>;
99 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z13_LSUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z13_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z13_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z13_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z13_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z13_VecUnit]>;
105 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z13_VecUnit]>;
H A DSystemZScheduleZ14.td73 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
97 def : WriteRes<!cast<SchedWrite>("FXa"#Num), [Z14_FXaUnit]>;
98 def : WriteRes<!cast<SchedWrite>("FXb"#Num), [Z14_FXbUnit]>;
99 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z14_LSUnit]>;
100 def : WriteRes<!cast<SchedWrite>("VecBF"#Num), [Z14_VecUnit]>;
101 def : WriteRes<!cast<SchedWrite>("VecDF"#Num), [Z14_VecUnit]>;
102 def : WriteRes<!cast<SchedWrite>("VecDFX"#Num), [Z14_VecUnit]>;
103 def : WriteRes<!cast<SchedWrite>("VecMul"#Num), [Z14_VecUnit]>;
104 def : WriteRes<!cast<SchedWrite>("VecStr"#Num), [Z14_VecUnit]>;
105 def : WriteRes<!cast<SchedWrite>("VecXsPm"#Num), [Z14_VecUnit]>;
H A DSystemZScheduleZEC12.td69 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
88 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [ZEC12_FXUnit]>;
89 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [ZEC12_LSUnit]>;
90 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [ZEC12_FPUnit]>;
91 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [ZEC12_DFUnit]>;
H A DSystemZScheduleZ196.td69 def : WriteRes<!cast<SchedWrite>("WLat"#L), []> { let Latency = L; }
87 def : WriteRes<!cast<SchedWrite>("FXU"#Num), [Z196_FXUnit]>;
88 def : WriteRes<!cast<SchedWrite>("LSU"#Num), [Z196_LSUnit]>;
89 def : WriteRes<!cast<SchedWrite>("FPU"#Num), [Z196_FPUnit]>;
90 def : WriteRes<!cast<SchedWrite>("DFU"#Num), [Z196_DFUnit]>;
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64Schedule.td21 def WriteImm : SchedWrite; // MOVN, MOVZ
25 def WriteI : SchedWrite; // ALU
33 def WriteIS : SchedWrite; // Shift/Scale
34 def WriteID32 : SchedWrite; // 32-bit Divide
35 def WriteID64 : SchedWrite; // 64-bit Divide
41 def WriteBr : SchedWrite; // Branch
63 def WriteLDHi : SchedWrite;
69 def WriteBarrier : SchedWrite; // Memory barrier.
80 def WriteV : SchedWrite; // Vector ops.
81 def WriteVLD : SchedWrite; // Vector loads.
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H A DAArch64SchedThunderX.td45 // Subtarget-specific SchedWrite types mapping the ProcResources and
H A DAArch64SchedA53.td50 // Subtarget-specific SchedWrite types which both map the ProcResources and
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86Schedule.td23 def WriteRMW : SchedWrite;
42 SchedWrite Folded;
51 def Ld : SchedWrite;
95 SchedWrite RR = MoveRR;
96 SchedWrite RM = LoadRM;
97 SchedWrite MR = StoreMR;
113 def WriteLoad : SchedWrite;
114 def WriteStore : SchedWrite;
196 def WriteZero : SchedWrite;
461 def WriteEMMS : SchedWrite;
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H A DX86SchedBroadwell.td572 …f : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
581 …WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
H A DX86SchedSkylakeClient.td572 … : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
581 …riteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
H A DX86SchedSkylakeServer.td573 … : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
582 …riteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
H A DX86InstrAVX512.td781 SchedWrite SchedRR, SchedWrite SchedMR> {
816 SchedWrite SchedRR, SchedWrite SchedMR> :
837 SchedWrite SchedRR, SchedWrite SchedMR> {
1125 SchedWrite SchedRR, SchedWrite SchedRM,
1187 SchedWrite SchedRR, SchedWrite SchedRM,
1240 multiclass avx512_int_broadcast_reg<bits<8> opc, SchedWrite SchedRR,
1251 multiclass avx512_int_broadcastbw_reg<bits<8> opc, string Name, SchedWrite SchedRR,
8936 X86MemOperand x86memop, SchedWrite RR, SchedWrite MR> {
8973 SchedWrite Sched> {
H A DX86ScheduleBdVer2.td191 multiclass PdWriteRes<SchedWrite SchedRW,
H A DX86InstrSSE.td7391 PatFrag ld_frag, SchedWrite Sched> :
7399 ValueType ResVT, ValueType OpVT, SchedWrite Sched> :
7746 SchedWrite RR, SchedWrite MR> {
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMSchedule.td61 def WriteALU : SchedWrite;
71 def WriteCMP : SchedWrite;
90 def WriteDIV : SchedWrite;
93 def WriteLd : SchedWrite;
95 def WriteST : SchedWrite;
98 def WriteBr : SchedWrite;
99 def WriteBrL : SchedWrite;
103 def WriteNoop : SchedWrite;
135 def WriteVLD1 : SchedWrite;
136 def WriteVLD2 : SchedWrite;
[all …]
H A DARMScheduleA9.td2087 [A9WriteLMLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2089 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2152 [A9WriteIssue, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2157 [A9WriteF, !cast<SchedWrite>("A9WriteLfp"#NumAddr#Seq)]>;
2187 [A9WriteLMfpLo, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
2192 [A9WriteLMHi, !cast<SchedWrite>("A9WriteCycle"#NumAddr)]>;
H A DARMScheduleR52.td57 // Subtarget-specific SchedWrite types which map ProcResources and set latency.
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSISchedule.td20 def WriteBranch : SchedWrite;
21 def WriteExport : SchedWrite;
22 def WriteLDS : SchedWrite;
23 def WriteSALU : SchedWrite;
24 def WriteSMEM : SchedWrite;
25 def WriteVMEM : SchedWrite;
26 def WriteBarrier : SchedWrite;
33 def WriteFloatFMA : SchedWrite;
36 def WriteDouble : SchedWrite;
39 def WriteDoubleAdd : SchedWrite;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td58 def WriteLD : SchedWrite;
59 def WriteST : SchedWrite;
60 def WriteLDSW : SchedWrite;
61 def WriteSTSW : SchedWrite;
62 def WriteALU : SchedWrite;
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSchedule.td222 // single SchedWrite and single SchedRead in any order.
228 class SchedWrite : SchedReadWrite;
229 def NoWrite : SchedWrite;
234 // Define a SchedWrite that is modeled as a sequence of other
244 class WriteSequence<list<SchedWrite> writes, int rep = 1> : SchedWrite {
245 list<SchedWrite> Writes = writes;
271 // SchedWrite is defined by the target, while WriteResources is
272 // defined by the subtarget, and maps the SchedWrite to processor
304 SchedWrite WriteType = write;
318 list<SchedWrite> ValidWrites = writes;
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/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp106 Record *FindWriteResources(const CodeGenSchedRW &SchedWrite,
808 const CodeGenSchedRW &SchedWrite, const CodeGenProcModel &ProcModel) { in FindWriteResources() argument
812 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
813 return SchedWrite.TheDef; in FindWriteResources()
816 for (Record *A : SchedWrite.Aliases) { in FindWriteResources()
839 || SchedWrite.TheDef == WR->getValueAsDef("WriteType")) { in FindWriteResources()
853 SchedWrite.TheDef->getName()); in FindWriteResources()
H A DCodeGenSchedule.cpp802 const CodeGenSchedRW &SchedWrite = getSchedRW(RWIdx, IsRead); in expandRWSeqForProc() local
804 for (const Record *Rec : SchedWrite.Aliases) { in expandRWSeqForProc()
822 if (!SchedWrite.IsSequence) { in expandRWSeqForProc()
827 SchedWrite.TheDef ? SchedWrite.TheDef->getValueAsInt("Repeat") : 1; in expandRWSeqForProc()
829 for (unsigned Idx : SchedWrite.Sequence) { in expandRWSeqForProc()