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Searched refs:SRsrc (Results 1 – 2 of 2) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp120 bool SelectMUBUF(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
124 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc, SDValue &VAddr,
127 bool SelectMUBUFAddr64(SDValue Addr, SDValue &SRsrc,
137 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &SOffset,
140 bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
1100 SRsrc = SDValue(Lowering.wrapAddr64Rsrc(*CurDAG, DL, Ptr), 0); in SelectMUBUFAddr64()
1211 SDValue &SRsrc, in SelectMUBUFScratchOffset() argument
1715 SDValue SRsrc, VAddr, SOffset, Offset, SLC; in SelectATOMIC_CMP_SWAP() local
1725 CmpVal, VAddr, SRsrc, SOffset, Offset, SLC, Mem->getChain() in SelectATOMIC_CMP_SWAP()
1733 SDValue SRsrc, SOffset, Offset, SLC; in SelectATOMIC_CMP_SWAP() local
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H A DSIInstrInfo.cpp3718 unsigned SRsrc = MRI.createVirtualRegister(&AMDGPU::SReg_128RegClass); in emitLoadSRsrcFromVGPRLoop() local
3730 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc) in emitLoadSRsrcFromVGPRLoop()
3741 Rsrc.setReg(SRsrc); in emitLoadSRsrcFromVGPRLoop()
3746 .addReg(SRsrc, 0, AMDGPU::sub0_sub1) in emitLoadSRsrcFromVGPRLoop()
3749 .addReg(SRsrc, 0, AMDGPU::sub2_sub3) in emitLoadSRsrcFromVGPRLoop()
4010 MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc); in legalizeOperands() local
4011 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) { in legalizeOperands()
4012 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI); in legalizeOperands()
4013 SRsrc->setReg(SGPR); in legalizeOperands()