Home
last modified time | relevance | path

Searched refs:SMLAL (Results 1 – 11 of 11) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.h202 SMLAL, // 64bit Signed Accumulate Multiply enumerator
H A DARMInstrInfo.td4161 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4193 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4346 // Halfword multiply accumulate long: SMLAL<x><y>.
4347 class SMLAL<bits<2> opc1, string asm>
4356 def SMLALBB : SMLAL<0b00, "smlalbb">;
4357 def SMLALBT : SMLAL<0b10, "smlalbt">;
4358 def SMLALTB : SMLAL<0b01, "smlaltb">;
4359 def SMLALTT : SMLAL<0b11, "smlaltt">;
6134 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6145 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
H A DARMScheduleSwift.td308 (instregex "SMLAL", "UMLAL", "SMLALBT",
H A DARMScheduleR52.td280 "SMLAL", "UMLAL", "SMLALBT",
H A DARMISelDAGToDAG.cpp2836 case ARMISD::SMLAL:{ in Select()
2850 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
H A DARMISelLowering.cpp1372 case ARMISD::SMLAL: return "ARMISD::SMLAL"; in getTargetNodeName()
10035 SDValue SMLAL = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), in AddCombineTo64BitSMLAL16() local
10038 SDValue HiMLALResult(SMLAL.getNode(), 1); in AddCombineTo64BitSMLAL16()
10039 SDValue LoMLALResult(SMLAL.getNode(), 0); in AddCombineTo64BitSMLAL16()
10128 unsigned FinalOpc = (Opc == ISD::SMUL_LOHI) ? ARMISD::SMLAL : ARMISD::UMLAL; in AddCombineTo64bitMLAL()
10178 FinalOpc == ARMISD::SMLAL && !AddeSubeNode->hasAnyUseOfValue(1) && in AddCombineTo64bitMLAL()
H A DARMScheduleA9.td2552 (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
H A DARMInstrFormats.td903 // SMLAL*
H A DARMInstrThumb2.td2818 // Halfword multiple accumulate long: SMLAL<x><y>
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td525 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
H A DAArch64InstrInfo.td4129 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
4176 // Additional patterns for SMLAL/SMLSL and UMLAL/UMLSL
5247 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",