1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999 5 * Bill Paul <[email protected]>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37 /* 38 * Registers for the Adaptec AIC-6915 Starfire. The Starfire has a 512K 39 * register space. These registers can be accessed in the following way: 40 * - PCI config registers are always accessible through PCI config space 41 * - Full 512K space mapped into memory using PCI memory mapped access 42 * - 256-byte I/O space mapped through PCI I/O access 43 * - Full 512K space mapped through indirect I/O using PCI I/O access 44 * It's possible to use either memory mapped mode or I/O mode to access 45 * the registers, but memory mapped is usually the easiest. All registers 46 * are 32 bits wide and must be accessed using 32-bit operations. 47 */ 48 49 /* 50 * Adaptec PCI vendor ID. 51 */ 52 #define AD_VENDORID 0x9004 53 54 /* 55 * AIC-6915 PCI device ID. 56 */ 57 #define AD_DEVICEID_STARFIRE 0x6915 58 59 /* 60 * AIC-6915 subsystem IDs. Adaptec uses the subsystem ID to identify 61 * the exact kind of NIC on which the ASIC is mounted. Currently there 62 * are six different variations. Note: the Adaptec manual lists code 0x28 63 * for two different NICs: the 62044 and the 69011/TX. This is a typo: 64 * the code for the 62044 is really 0x18. 65 * 66 * Note that there also appears to be an 0x19 code for a newer rev 67 * 62044 card. 68 */ 69 #define AD_SUBSYSID_62011_REV0 0x0008 /* single port 10/100baseTX 64-bit */ 70 #define AD_SUBSYSID_62011_REV1 0x0009 /* single port 10/100baseTX 64-bit */ 71 #define AD_SUBSYSID_62022 0x0010 /* dual port 10/100baseTX 64-bit */ 72 #define AD_SUBSYSID_62044_REV0 0x0018 /* quad port 10/100baseTX 64-bit */ 73 #define AD_SUBSYSID_62044_REV1 0x0019 /* quad port 10/100baseTX 64-bit */ 74 #define AD_SUBSYSID_62020 0x0020 /* single port 10/100baseFX 64-bit */ 75 #define AD_SUBSYSID_69011 0x0028 /* single port 10/100baseTX 32-bit */ 76 77 /* 78 * Starfire internal register space map. The entire register space 79 * is available using PCI memory mapped mode. The SF_RMAP_INTREG 80 * space is available using PCI I/O mode. The entire space can be 81 * accessed using indirect I/O using the indirect I/O addr and 82 * indirect I/O data registers located within the SF_RMAP_INTREG space. 83 */ 84 #define SF_RMAP_ROMADDR_BASE 0x00000 /* Expansion ROM space */ 85 #define SF_RMAP_ROMADDR_MAX 0x3FFFF 86 87 #define SF_RMAP_EXGPIO_BASE 0x40000 /* External general purpose regs */ 88 #define SF_RMAP_EXGPIO_MAX 0x3FFFF 89 90 #define SF_RMAP_INTREG_BASE 0x50000 /* Internal functional registers */ 91 #define SF_RMAP_INTREG_MAX 0x500FF 92 #define SF_RMAP_GENREG_BASE 0x50100 /* General purpose registers */ 93 #define SF_RMAP_GENREG_MAX 0x5FFFF 94 95 #define SF_RMAP_FIFO_BASE 0x60000 96 #define SF_RMAP_FIFO_MAX 0x6FFFF 97 98 #define SF_RMAP_STS_BASE 0x70000 99 #define SF_RMAP_STS_MAX 0x70083 100 101 #define SF_RMAP_RSVD_BASE 0x70084 102 #define SF_RMAP_RSVD_MAX 0x7FFFF 103 104 /* 105 * PCI config header registers, 0x0000 to 0x003F 106 */ 107 #define SF_PCI_VENDOR_ID 0x0000 108 #define SF_PCI_DEVICE_ID 0x0002 109 #define SF_PCI_COMMAND 0x0004 110 #define SF_PCI_STATUS 0x0006 111 #define SF_PCI_REVID 0x0008 112 #define SF_PCI_CLASSCODE 0x0009 113 #define SF_PCI_CACHELEN 0x000C 114 #define SF_PCI_LATENCY_TIMER 0x000D 115 #define SF_PCI_HEADER_TYPE 0x000E 116 #define SF_PCI_LOMEM 0x0010 117 #define SF_PCI_LOIO 0x0014 118 #define SF_PCI_SUBVEN_ID 0x002C 119 #define SF_PCI_SYBSYS_ID 0x002E 120 #define SF_PCI_BIOSROM 0x0030 121 #define SF_PCI_INTLINE 0x003C 122 #define SF_PCI_INTPIN 0x003D 123 #define SF_PCI_MINGNT 0x003E 124 #define SF_PCI_MINLAT 0x003F 125 126 /* 127 * PCI registers, 0x0040 to 0x006F 128 */ 129 #define SF_PCI_DEVCFG 0x0040 130 #define SF_BACCTL 0x0044 131 #define SF_PCI_MON1 0x0048 132 #define SF_PCI_MON2 0x004C 133 #define SF_PCI_CAPID 0x0050 /* 8 bits */ 134 #define SF_PCI_NEXTPTR 0x0051 /* 8 bits */ 135 #define SF_PCI_PWRMGMTCAP 0x0052 /* 16 bits */ 136 #define SF_PCI_PWRMGMTCTRL 0x0054 /* 16 bits */ 137 #define SF_PCI_PME_EVENT 0x0058 138 #define SF_PCI_EECTL 0x0060 139 #define SF_PCI_COMPLIANCE 0x0064 140 #define SF_INDIRECTIO_ADDR 0x0068 141 #define SF_INDIRECTIO_DATA 0x006C 142 143 #define SF_PCIDEVCFG_RESET 0x00000001 144 #define SF_PCIDEVCFG_FORCE64 0x00000002 145 #define SF_PCIDEVCFG_SYSTEM64 0x00000004 146 #define SF_PCIDEVCFG_RSVD0 0x00000008 147 #define SF_PCIDEVCFG_INCR_INB 0x00000010 148 #define SF_PCIDEVCFG_ABTONPERR 0x00000020 149 #define SF_PCIDEVCFG_STPONPERR 0x00000040 150 #define SF_PCIDEVCFG_MR_ENB 0x00000080 151 #define SF_PCIDEVCFG_FIFOTHR 0x00000F00 152 #define SF_PCIDEVCFG_STPONCA 0x00001000 153 #define SF_PCIDEVCFG_PCIMEN 0x00002000 /* enable PCI bus master */ 154 #define SF_PCIDEVCFG_LATSTP 0x00004000 155 #define SF_PCIDEVCFG_BYTE_ENB 0x00008000 156 #define SF_PCIDEVCFG_EECSWIDTH 0x00070000 157 #define SF_PCIDEVCFG_STPMWCA 0x00080000 158 #define SF_PCIDEVCFG_REGCSWIDTH 0x00700000 159 #define SF_PCIDEVCFG_INTR_ENB 0x00800000 160 #define SF_PCIDEVCFG_DPR_ENB 0x01000000 161 #define SF_PCIDEVCFG_RSVD1 0x02000000 162 #define SF_PCIDEVCFG_RSVD2 0x04000000 163 #define SF_PCIDEVCFG_STA_ENB 0x08000000 164 #define SF_PCIDEVCFG_RTA_ENB 0x10000000 165 #define SF_PCIDEVCFG_RMA_ENB 0x20000000 166 #define SF_PCIDEVCFG_SSE_ENB 0x40000000 167 #define SF_PCIDEVCFG_DPE_ENB 0x80000000 168 169 #define SF_BACCTL_BACDMA_ENB 0x00000001 170 #define SF_BACCTL_PREFER_RXDMA 0x00000002 171 #define SF_BACCTL_PREFER_TXDMA 0x00000004 172 #define SF_BACCTL_SINGLE_DMA 0x00000008 173 #define SF_BACCTL_SWAPMODE_DATA 0x00000030 174 #define SF_BACCTL_SWAPMODE_DESC 0x000000C0 175 176 #define SF_SWAPMODE_LE 0x00000000 177 #define SF_SWAPMODE_BE 0x00000010 178 179 #define SF_PSTATE_MASK 0x0003 180 #define SF_PSTATE_D0 0x0000 181 #define SF_PSTATE_D1 0x0001 182 #define SF_PSTATE_D2 0x0002 183 #define SF_PSTATE_D3 0x0003 184 #define SF_PME_EN 0x0010 185 #define SF_PME_STATUS 0x8000 186 187 188 /* 189 * Ethernet registers 0x0070 to 0x00FF 190 */ 191 #define SF_GEN_ETH_CTL 0x0070 192 #define SF_TIMER_CTL 0x0074 193 #define SF_CURTIME 0x0078 194 #define SF_ISR 0x0080 195 #define SF_ISR_SHADOW 0x0084 196 #define SF_IMR 0x0088 197 #define SF_GPIO 0x008C 198 #define SF_TXDQ_CTL 0x0090 199 #define SF_TXDQ_ADDR_HIPRIO 0x0094 200 #define SF_TXDQ_ADDR_LOPRIO 0x0098 201 #define SF_TXDQ_ADDR_HI 0x009C 202 #define SF_TXDQ_PRODIDX 0x00A0 203 #define SF_TXDQ_CONSIDX 0x00A4 204 #define SF_TXDMA_STS1 0x00A8 205 #define SF_TXDMA_STS2 0x00AC 206 #define SF_TX_FRAMCTL 0x00B0 207 #define SF_CQ_ADDR_HI 0x00B4 208 #define SF_TXCQ_CTL 0x00B8 209 #define SF_RXCQ_CTL_1 0x00BC 210 #define SF_RXCQ_CTL_2 0x00C0 211 #define SF_CQ_CONSIDX 0x00C4 212 #define SF_CQ_PRODIDX 0x00C8 213 #define SF_CQ_RXQ2 0x00CC 214 #define SF_RXDMA_CTL 0x00D0 215 #define SF_RXDQ_CTL_1 0x00D4 216 #define SF_RXDQ_CTL_2 0x00D8 217 #define SF_RXDQ_ADDR_HI 0x00DC 218 #define SF_RXDQ_ADDR_Q1 0x00E0 219 #define SF_RXDQ_ADDR_Q2 0x00E4 220 #define SF_RXDQ_PTR_Q1 0x00E8 221 #define SF_RXDQ_PTR_Q2 0x00EC 222 #define SF_RXDMA_STS 0x00F0 223 #define SF_RXFILT 0x00F4 224 #define SF_RX_FRAMETEST_OUT 0x00F8 225 226 /* Ethernet control register */ 227 #define SF_ETHCTL_RX_ENB 0x00000001 228 #define SF_ETHCTL_TX_ENB 0x00000002 229 #define SF_ETHCTL_RXDMA_ENB 0x00000004 230 #define SF_ETHCTL_TXDMA_ENB 0x00000008 231 #define SF_ETHCTL_RXGFP_ENB 0x00000010 232 #define SF_ETHCTL_TXGFP_ENB 0x00000020 233 #define SF_ETHCTL_SOFTINTR 0x00000800 234 235 /* Timer control register */ 236 #define SF_TIMER_IMASK_INTERVAL 0x0000001F 237 #define SF_TIMER_IMASK_MODE 0x00000060 238 #define SF_TIMER_SMALLFRAME_BYP 0x00000100 239 #define SF_TIMER_SMALLRX_FRAME 0x00000600 240 #define SF_TIMER_TIMES_TEN 0x00000800 241 #define SF_TIMER_RXHIPRIO_BYP 0x00001000 242 #define SF_TIMER_TX_DMADONE_DLY 0x00002000 243 #define SF_TIMER_TX_QDONE_DLY 0x00004000 244 #define SF_TIMER_TX_FRDONE_DLY 0x00008000 245 #define SF_TIMER_GENTIMER 0x00FF0000 246 #define SF_TIMER_ONESHOT 0x01000000 247 #define SF_TIMER_GENTIMER_RES 0x02000000 248 #define SF_TIMER_TIMEST_RES 0x04000000 249 #define SF_TIMER_RXQ2DONE_DLY 0x10000000 250 #define SF_TIMER_EARLYRX2_DLY 0x20000000 251 #define SF_TIMER_RXQ1DONE_DLY 0x40000000 252 #define SF_TIMER_EARLYRX1_DLY 0x80000000 253 254 /* Timer resolution is 0.8us * 128. */ 255 #define SF_IM_MIN 0 256 #define SF_IM_MAX 0x1F /* 3.276ms */ 257 #define SF_IM_DEFAULT 1 /* 102.4us */ 258 259 /* Interrupt status register */ 260 #define SF_ISR_PCIINT_ASSERTED 0x00000001 261 #define SF_ISR_GFP_TX 0x00000002 262 #define SF_ISR_GFP_RX 0x00000004 263 #define SF_ISR_TX_BADID_HIPRIO 0x00000008 264 #define SF_ISR_TX_BADID_LOPRIO 0x00000010 265 #define SF_ISR_NO_TX_CSUM 0x00000020 266 #define SF_ISR_RXDQ2_NOBUFS 0x00000040 267 #define SF_ISR_RXGFP_NORESP 0x00000080 268 #define SF_ISR_RXDQ1_DMADONE 0x00000100 269 #define SF_ISR_RXDQ2_DMADONE 0x00000200 270 #define SF_ISR_RXDQ1_EARLY 0x00000400 271 #define SF_ISR_RXDQ2_EARLY 0x00000800 272 #define SF_ISR_TX_QUEUEDONE 0x00001000 273 #define SF_ISR_TX_DMADONE 0x00002000 274 #define SF_ISR_TX_TXDONE 0x00004000 275 #define SF_ISR_NORMALINTR 0x00008000 276 #define SF_ISR_RXDQ1_NOBUFS 0x00010000 277 #define SF_ISR_RXCQ2_NOBUFS 0x00020000 278 #define SF_ISR_TX_LOFIFO 0x00040000 279 #define SF_ISR_DMAERR 0x00080000 280 #define SF_ISR_PCIINT 0x00100000 281 #define SF_ISR_TXCQ_NOBUFS 0x00200000 282 #define SF_ISR_RXCQ1_NOBUFS 0x00400000 283 #define SF_ISR_SOFTINTR 0x00800000 284 #define SF_ISR_GENTIMER 0x01000000 285 #define SF_ISR_ABNORMALINTR 0x02000000 286 #define SF_ISR_RSVD0 0x04000000 287 #define SF_ISR_STATSOFLOW 0x08000000 288 #define SF_ISR_GPIO 0xF0000000 289 290 /* 291 * Shadow interrupt status register. Unlike the normal IRQ register, 292 * reading bits here does not automatically cause them to reset. 293 */ 294 #define SF_SISR_PCIINT_ASSERTED 0x00000001 295 #define SF_SISR_GFP_TX 0x00000002 296 #define SF_SISR_GFP_RX 0x00000004 297 #define SF_SISR_TX_BADID_HIPRIO 0x00000008 298 #define SF_SISR_TX_BADID_LOPRIO 0x00000010 299 #define SF_SISR_NO_TX_CSUM 0x00000020 300 #define SF_SISR_RXDQ2_NOBUFS 0x00000040 301 #define SF_SISR_RXGFP_NORESP 0x00000080 302 #define SF_SISR_RXDQ1_DMADONE 0x00000100 303 #define SF_SISR_RXDQ2_DMADONE 0x00000200 304 #define SF_SISR_RXDQ1_EARLY 0x00000400 305 #define SF_SISR_RXDQ2_EARLY 0x00000800 306 #define SF_SISR_TX_QUEUEDONE 0x00001000 307 #define SF_SISR_TX_DMADONE 0x00002000 308 #define SF_SISR_TX_TXDONE 0x00004000 309 #define SF_SISR_NORMALINTR 0x00008000 310 #define SF_SISR_RXDQ1_NOBUFS 0x00010000 311 #define SF_SISR_RXCQ2_NOBUFS 0x00020000 312 #define SF_SISR_TX_LOFIFO 0x00040000 313 #define SF_SISR_DMAERR 0x00080000 314 #define SF_SISR_PCIINT 0x00100000 315 #define SF_SISR_TXCQ_NOBUFS 0x00200000 316 #define SF_SISR_RXCQ1_NOBUFS 0x00400000 317 #define SF_SISR_SOFTINTR 0x00800000 318 #define SF_SISR_GENTIMER 0x01000000 319 #define SF_SISR_ABNORMALINTR 0x02000000 320 #define SF_SISR_RSVD0 0x04000000 321 #define SF_SISR_STATSOFLOW 0x08000000 322 #define SF_SISR_GPIO 0xF0000000 323 324 /* Interrupt mask register */ 325 #define SF_IMR_PCIINT_ASSERTED 0x00000001 326 #define SF_IMR_GFP_TX 0x00000002 327 #define SF_IMR_GFP_RX 0x00000004 328 #define SF_IMR_TX_BADID_HIPRIO 0x00000008 329 #define SF_IMR_TX_BADID_LOPRIO 0x00000010 330 #define SF_IMR_NO_TX_CSUM 0x00000020 331 #define SF_IMR_RXDQ2_NOBUFS 0x00000040 332 #define SF_IMR_RXGFP_NORESP 0x00000080 333 #define SF_IMR_RXDQ1_DMADONE 0x00000100 334 #define SF_IMR_RXDQ2_DMADONE 0x00000200 335 #define SF_IMR_RXDQ1_EARLY 0x00000400 336 #define SF_IMR_RXDQ2_EARLY 0x00000800 337 #define SF_IMR_TX_QUEUEDONE 0x00001000 338 #define SF_IMR_TX_DMADONE 0x00002000 339 #define SF_IMR_TX_TXDONE 0x00004000 340 #define SF_IMR_NORMALINTR 0x00008000 341 #define SF_IMR_RXDQ1_NOBUFS 0x00010000 342 #define SF_IMR_RXCQ2_NOBUFS 0x00020000 343 #define SF_IMR_TX_LOFIFO 0x00040000 344 #define SF_IMR_DMAERR 0x00080000 345 #define SF_IMR_PCIINT 0x00100000 346 #define SF_IMR_TXCQ_NOBUFS 0x00200000 347 #define SF_IMR_RXCQ1_NOBUFS 0x00400000 348 #define SF_IMR_SOFTINTR 0x00800000 349 #define SF_IMR_GENTIMER 0x01000000 350 #define SF_IMR_ABNORMALINTR 0x02000000 351 #define SF_IMR_RSVD0 0x04000000 352 #define SF_IMR_STATSOFLOW 0x08000000 353 #define SF_IMR_GPIO 0xF0000000 354 355 #define SF_INTRS \ 356 (SF_IMR_RXDQ2_NOBUFS|SF_IMR_RXDQ1_DMADONE|SF_IMR_RXDQ2_DMADONE| \ 357 SF_IMR_TX_DMADONE|SF_IMR_RXDQ1_NOBUFS| \ 358 SF_IMR_NORMALINTR|SF_IMR_ABNORMALINTR|SF_IMR_TXCQ_NOBUFS| \ 359 SF_IMR_RXCQ1_NOBUFS|SF_IMR_RXCQ2_NOBUFS|SF_IMR_STATSOFLOW| \ 360 SF_IMR_TX_LOFIFO|SF_IMR_DMAERR|SF_IMR_RXGFP_NORESP| \ 361 SF_IMR_NO_TX_CSUM) 362 363 /* TX descriptor queue control registers */ 364 #define SF_TXDQCTL_DESCTYPE 0x00000007 365 #define SF_TXDQCTL_NODMACMP 0x00000008 366 #define SF_TXDQCTL_MINSPACE 0x00000070 367 #define SF_TXDQCTL_64BITADDR 0x00000080 368 #define SF_TXDQCTL_BURSTLEN 0x00003F00 369 #define SF_TXDQCTL_SKIPLEN 0x001F0000 370 #define SF_TXDQCTL_HIPRIOTHRESH 0xFF000000 371 372 #define SF_TXDMA_HIPRIO_THRESH 2 373 #define SF_TXDDMA_BURST (128 / 32) 374 375 #define SF_TXBUFDESC_TYPE0 0x00000000 376 #define SF_TXBUFDESC_TYPE1 0x00000001 377 #define SF_TXBUFDESC_TYPE2 0x00000002 378 #define SF_TXBUFDESC_TYPE3 0x00000003 379 #define SF_TXBUFDESC_TYPE4 0x00000004 380 381 #define SF_TXMINSPACE_UNLIMIT 0x00000000 382 #define SF_TXMINSPACE_32BYTES 0x00000010 383 #define SF_TXMINSPACE_64BYTES 0x00000020 384 #define SF_TXMINSPACE_128BYTES 0x00000030 385 #define SF_TXMINSPACE_256BYTES 0x00000040 386 387 #define SF_TXSKIPLEN_0BYTES 0x00000000 388 #define SF_TXSKIPLEN_8BYTES 0x00010000 389 #define SF_TXSKIPLEN_16BYTES 0x00020000 390 #define SF_TXSKIPLEN_24BYTES 0x00030000 391 #define SF_TXSKIPLEN_32BYTES 0x00040000 392 393 /* TX frame control register */ 394 #define SF_TXFRMCTL_TXTHRESH 0x000000FF 395 #define SF_TXFRMCTL_CPLAFTERTX 0x00000100 396 #define SF_TXFRMCRL_DEBUG 0x0000FE00 397 #define SF_TXFRMCTL_STATUS 0x01FF0000 398 #define SF_TXFRMCTL_MAC_TXIF 0xFE000000 399 400 /* TX completion queue control register */ 401 #define SF_TXCQ_THRESH 0x0000000F 402 #define SF_TXCQ_COMMON 0x00000010 403 #define SF_TXCQ_SIZE 0x00000020 404 #define SF_TXCQ_WRITEENB 0x00000040 405 #define SF_TXCQ_USE_64BIT 0x00000080 406 #define SF_TXCQ_ADDR 0xFFFFFF00 407 408 /* RX completion queue control register */ 409 #define SF_RXCQ_THRESH 0x0000000F 410 #define SF_RXCQ_TYPE 0x00000030 411 #define SF_RXCQ_WRITEENB 0x00000040 412 #define SF_RXCQ_USE_64BIT 0x00000080 413 #define SF_RXCQ_ADDR 0xFFFFFF00 414 415 #define SF_RXCQTYPE_0 0x00000000 416 #define SF_RXCQTYPE_1 0x00000010 417 #define SF_RXCQTYPE_2 0x00000020 418 #define SF_RXCQTYPE_3 0x00000030 419 420 /* TX descriptor queue producer index register */ 421 #define SF_TXDQ_PRODIDX_LOPRIO 0x000007FF 422 #define SF_TXDQ_PRODIDX_HIPRIO 0x07FF0000 423 424 /* TX descriptor queue consumer index register */ 425 #define SF_TXDQ_CONSIDX_LOPRIO 0x000007FF 426 #define SF_TXDQ_CONSIDX_HIPRIO 0x07FF0000 427 428 /* Completion queue consumer index register */ 429 #define SF_CQ_CONSIDX_RXQ1 0x000003FF 430 #define SF_CQ_CONSIDX_RXTHRMODE 0x00008000 431 #define SF_CQ_CONSIDX_TXQ 0x03FF0000 432 #define SF_CQ_CONSIDX_TXTHRMODE 0x80000000 433 434 /* Completion queue producer index register */ 435 #define SF_CQ_PRODIDX_RXQ1 0x000003FF 436 #define SF_CQ_PRODIDX_TXQ 0x03FF0000 437 438 /* RX completion queue 2 consumer/producer index register */ 439 #define SF_CQ_RXQ2_CONSIDX 0x000003FF 440 #define SF_CQ_RXQ2_RXTHRMODE 0x00008000 441 #define SF_CQ_RXQ2_PRODIDX 0x03FF0000 442 443 #define SF_CQ_RXTHRMODE_INT_ON 0x00008000 444 #define SF_CQ_RXTHRMODE_INT_OFF 0x00000000 445 #define SF_CQ_TXTHRMODE_INT_ON 0x80000000 446 #define SF_CQ_TXTHRMODE_INT_OFF 0x00000000 447 448 /* RX DMA control register */ 449 #define SF_RXDMA_BURSTSIZE 0x0000007F 450 #define SF_RXDMA_FPTESTMODE 0x00000080 451 #define SF_RXDMA_HIPRIOTHRESH 0x00000F00 452 #define SF_RXDMA_RXEARLYTHRESH 0x0001F000 453 #define SF_RXDMA_DMACRC 0x00040000 454 #define SF_RXDMA_USEBKUPQUEUE 0x00080000 455 #define SF_RXDMA_QUEUEMODE 0x00700000 456 #define SF_RXDMA_RXCQ2_ON 0x00800000 457 #define SF_RXDMA_CSUMMODE 0x03000000 458 #define SF_RXDMA_DMAPAUSEPKTS 0x04000000 459 #define SF_RXDMA_DMACTLPKTS 0x08000000 460 #define SF_RXDMA_DMACRXERRPKTS 0x10000000 461 #define SF_RXDMA_DMABADPKTS 0x20000000 462 #define SF_RXDMA_DMARUNTS 0x40000000 463 #define SF_RXDMA_REPORTBADPKTS 0x80000000 464 #define SF_RXDMA_HIGHPRIO_THRESH 6 465 #define SF_RXDMA_BURST (64 / 32) 466 467 #define SF_RXDQMODE_Q1ONLY 0x00100000 468 #define SF_RXDQMODE_Q2_ON_FP 0x00200000 469 #define SF_RXDQMODE_Q2_ON_SHORT 0x00300000 470 #define SF_RXDQMODE_Q2_ON_PRIO 0x00400000 471 #define SF_RXDQMODE_SPLITHDR 0x00500000 472 473 #define SF_RXCSUMMODE_IGNORE 0x00000000 474 #define SF_RXCSUMMODE_REJECT_BAD_TCP 0x01000000 475 #define SF_RXCSUMMODE_REJECT_BAD_TCPUDP 0x02000000 476 #define SF_RXCSUMMODE_RSVD 0x03000000 477 478 /* RX descriptor queue control registers */ 479 #define SF_RXDQCTL_MINDESCTHR 0x0000007F 480 #define SF_RXDQCTL_Q1_WE 0x00000080 481 #define SF_RXDQCTL_DESCSPACE 0x00000700 482 #define SF_RXDQCTL_64BITDADDR 0x00000800 483 #define SF_RXDQCTL_64BITBADDR 0x00001000 484 #define SF_RXDQCTL_VARIABLE 0x00002000 485 #define SF_RXDQCTL_ENTRIES 0x00004000 486 #define SF_RXDQCTL_PREFETCH 0x00008000 487 #define SF_RXDQCTL_BUFLEN 0xFFFF0000 488 489 #define SF_DESCSPACE_4BYTES 0x00000000 490 #define SF_DESCSPACE_8BYTES 0x00000100 491 #define SF_DESCSPACE_16BYTES 0x00000200 492 #define SF_DESCSPACE_32BYTES 0x00000300 493 #define SF_DESCSPACE_64BYTES 0x00000400 494 #define SF_DESCSPACE_128_BYTES 0x00000500 495 496 /* RX buffer consumer/producer index registers */ 497 #define SF_RXDQ_PRODIDX 0x000007FF 498 #define SF_RXDQ_CONSIDX 0x07FF0000 499 500 /* RX filter control register */ 501 #define SF_RXFILT_PROMISC 0x00000001 502 #define SF_RXFILT_ALLMULTI 0x00000002 503 #define SF_RXFILT_BROAD 0x00000004 504 #define SF_RXFILT_HASHPRIO 0x00000008 505 #define SF_RXFILT_HASHMODE 0x00000030 506 #define SF_RXFILT_PERFMODE 0x000000C0 507 #define SF_RXFILT_VLANMODE 0x00000300 508 #define SF_RXFILT_WAKEMODE 0x00000C00 509 #define SF_RXFILT_MULTI_NOBROAD 0x00001000 510 #define SF_RXFILT_MIN_VLANPRIO 0x0000E000 511 #define SF_RXFILT_PEFECTPRIO 0xFFFF0000 512 513 /* Hash filtering mode */ 514 #define SF_HASHMODE_OFF 0x00000000 515 #define SF_HASHMODE_WITHVLAN 0x00000010 516 #define SF_HASHMODE_ANYVLAN 0x00000020 517 #define SF_HASHMODE_ANY 0x00000030 518 519 /* Perfect filtering mode */ 520 #define SF_PERFMODE_OFF 0x00000000 521 #define SF_PERFMODE_NORMAL 0x00000040 522 #define SF_PERFMODE_INVERSE 0x00000080 523 #define SF_PERFMODE_VLAN 0x000000C0 524 525 /* VLAN mode */ 526 #define SF_VLANMODE_OFF 0x00000000 527 #define SF_VLANMODE_NOSTRIP 0x00000100 528 #define SF_VLANMODE_STRIP 0x00000200 529 #define SF_VLANMODE_RSVD 0x00000300 530 531 /* Wakeup mode */ 532 #define SF_WAKEMODE_OFF 0x00000000 533 #define SF_WAKEMODE_FILTER 0x00000400 534 #define SF_WAKEMODE_FP 0x00000800 535 #define SF_WAKEMODE_HIPRIO 0x00000C00 536 537 /* 538 * Extra PCI registers 0x0100 to 0x0FFF 539 */ 540 #define SF_PCI_TARGSTAT 0x0100 541 #define SF_PCI_MASTSTAT1 0x0104 542 #define SF_PCI_MASTSTAT2 0x0108 543 #define SF_PCI_DMAHOSTADDR_LO 0x010C 544 #define SF_BAC_DMADIAG0 0x0110 545 #define SF_BAC_DMADIAG1 0x0114 546 #define SF_BAC_DMADIAG2 0x0118 547 #define SF_BAC_DMADIAG3 0x011C 548 #define SF_PAR0 0x0120 549 #define SF_PAR1 0x0124 550 #define SF_PCICB_FUNCEVENT 0x0130 551 #define SF_PCICB_FUNCEVENT_MASK 0x0134 552 #define SF_PCICB_FUNCSTATE 0x0138 553 #define SF_PCICB_FUNCFORCE 0x013C 554 555 /* 556 * Serial EEPROM registers 0x1000 to 0x1FFF 557 * Presumeably the EEPROM is mapped into this 8K window. 558 */ 559 #define SF_EEADDR_BASE 0x1000 560 #define SF_EEADDR_MAX 0x1FFF 561 562 #define SF_EE_NODEADDR 14 563 564 /* 565 * MII registers registers 0x2000 to 0x3FFF 566 * There are 32 sets of 32 registers, one set for each possible 567 * PHY address. Each 32 bit register is split into a 16-bit data 568 * port and a couple of status bits. 569 */ 570 571 #define SF_MIIADDR_BASE 0x2000 572 #define SF_MIIADDR_MAX 0x3FFF 573 #define SF_MII_BLOCKS 32 574 575 #define SF_MII_DATAVALID 0x80000000 576 #define SF_MII_BUSY 0x40000000 577 #define SF_MII_DATAPORT 0x0000FFFF 578 579 #define SF_PHY_REG(phy, reg) \ 580 (SF_MIIADDR_BASE + ((phy) * SF_MII_BLOCKS * sizeof(uint32_t)) + \ 581 ((reg) * sizeof(uint32_t))) 582 583 /* 584 * Ethernet extra registers 0x4000 to 0x4FFF 585 */ 586 #define SF_TESTMODE 0x4000 587 #define SF_RX_FRAMEPROC_CTL 0x4004 588 #define SF_TX_FRAMEPROC_CTL 0x4008 589 590 /* 591 * MAC registers 0x5000 to 0x5FFF 592 */ 593 #define SF_MACCFG_1 0x5000 594 #define SF_MACCFG_2 0x5004 595 #define SF_BKTOBKIPG 0x5008 596 #define SF_NONBKTOBKIPG 0x500C 597 #define SF_COLRETRY 0x5010 598 #define SF_MAXLEN 0x5014 599 #define SF_TXNIBBLECNT 0x5018 600 #define SF_TXBYTECNT 0x501C 601 #define SF_RETXCNT 0x5020 602 #define SF_RANDNUM 0x5024 603 #define SF_RANDNUM_MASK 0x5028 604 #define SF_TOTALTXCNT 0x5034 605 #define SF_RXBYTECNT 0x5040 606 #define SF_TXPAUSETIMER 0x5060 607 #define SF_VLANTYPE 0x5064 608 #define SF_MIISTATUS 0x5070 609 610 #define SF_MACCFG1_HUGEFRAMES 0x00000001 611 #define SF_MACCFG1_FULLDUPLEX 0x00000002 612 #define SF_MACCFG1_AUTOPAD 0x00000004 613 #define SF_MACCFG1_HDJAM 0x00000008 614 #define SF_MACCFG1_DELAYCRC 0x00000010 615 #define SF_MACCFG1_NOBACKOFF 0x00000020 616 #define SF_MACCFG1_LENGTHCHECK 0x00000040 617 #define SF_MACCFG1_PUREPREAMBLE 0x00000080 618 #define SF_MACCFG1_PASSALLRX 0x00000100 619 #define SF_MACCFG1_PREAM_DETCNT 0x00000200 620 #define SF_MACCFG1_RX_FLOWENB 0x00000400 621 #define SF_MACCFG1_TX_FLOWENB 0x00000800 622 #define SF_MACCFG1_TESTMODE 0x00003000 623 #define SF_MACCFG1_MIILOOPBK 0x00004000 624 #define SF_MACCFG1_SOFTRESET 0x00008000 625 626 #define SF_MACCFG2_AUTOVLANPAD 0x00000020 627 628 /* 629 * There are the recommended IPG nibble counter settings 630 * specified in the Adaptec manual for full duplex and 631 * half duplex operation. 632 */ 633 #define SF_IPGT_FDX 0x15 634 #define SF_IPGT_HDX 0x11 635 636 /* 637 * RX filter registers 0x6000 to 0x6FFF 638 */ 639 #define SF_RXFILT_PERFECT_BASE 0x6000 640 #define SF_RXFILT_PERFECT_MAX 0x60FF 641 #define SF_RXFILT_PERFECT_SKIP 0x0010 642 #define SF_RXFILT_PERFECT_CNT 0x0010 643 644 #define SF_RXFILT_HASH_BASE 0x6100 645 #define SF_RXFILT_HASH_MAX 0x62FF 646 #define SF_RXFILT_HASH_SKIP 0x0010 647 #define SF_RXFILT_HASH_CNT 0x001F 648 #define SF_RXFILT_HASH_ADDROFF 0x0000 649 #define SF_RXFILT_HASH_PRIOOFF 0x0004 650 #define SF_RXFILT_HASH_VLANOFF 0x0008 651 652 /* 653 * Statistics registers 0x7000 to 0x7FFF 654 */ 655 #define SF_STATS_BASE 0x7000 656 #define SF_STATS_END 0x7FFF 657 658 #define SF_STATS_TX_FRAMES 0x0000 659 #define SF_STATS_TX_SINGLE_COL 0x0004 660 #define SF_STATS_TX_MULTI_COL 0x0008 661 #define SF_STATS_TX_CRC_ERRS 0x000C 662 #define SF_STATS_TX_BYTES 0x0010 663 #define SF_STATS_TX_DEFERRED 0x0014 664 #define SF_STATS_TX_LATE_COL 0x0018 665 #define SF_STATS_TX_PAUSE 0x001C 666 #define SF_STATS_TX_CTL_FRAME 0x0020 667 #define SF_STATS_TX_EXCESS_COL 0x0024 668 #define SF_STATS_TX_EXCESS_DEF 0x0028 669 #define SF_STATS_TX_MULTI 0x002C 670 #define SF_STATS_TX_BCAST 0x0030 671 #define SF_STATS_TX_FRAME_LOST 0x0034 672 #define SF_STATS_RX_FRAMES 0x0038 673 #define SF_STATS_RX_CRC_ERRS 0x003C 674 #define SF_STATS_RX_ALIGN_ERRS 0x0040 675 #define SF_STATS_RX_BYTES 0x0044 676 #define SF_STATS_RX_PAUSE 0x0048 677 #define SF_STATS_RX_CTL_FRAME 0x004C 678 #define SF_STATS_RX_UNSUP_FRAME 0x0050 679 #define SF_STATS_RX_GIANTS 0x0054 680 #define SF_STATS_RX_RUNTS 0x0058 681 #define SF_STATS_RX_JABBER 0x005C 682 #define SF_STATS_RX_FRAGMENTS 0x0060 683 #define SF_STATS_RX_64 0x0064 684 #define SF_STATS_RX_65_127 0x0068 685 #define SF_STATS_RX_128_255 0x006C 686 #define SF_STATS_RX_256_511 0x0070 687 #define SF_STATS_RX_512_1023 0x0074 688 #define SF_STATS_RX_1024_1518 0x0078 689 #define SF_STATS_RX_FRAME_LOST 0x007C 690 #define SF_STATS_TX_UNDERRUN 0x0080 691 692 /* 693 * TX frame processor instruction space 0x8000 to 0x9FFF 694 */ 695 #define SF_TXGFP_MEM_BASE 0x8000 696 #define SF_TXGFP_MEM_END 0x8FFF 697 698 /* Number of bytes of an GFP instruction. */ 699 #define SF_GFP_INST_BYTES 6 700 /* 701 * RX frame processor instruction space 0xA000 to 0xBFFF 702 */ 703 #define SF_RXGFP_MEM_BASE 0xA000 704 #define SF_RXGFP_MEM_END 0xBFFF 705 706 /* 707 * Ethernet FIFO access space 0xC000 to 0xDFFF 708 */ 709 710 /* 711 * Reserved 0xE000 to 0xFFFF 712 */ 713 714 /* 715 * Descriptor data structures. 716 */ 717 718 /* 719 * RX buffer descriptor type 0, 32-bit addressing. 720 */ 721 struct sf_rx_bufdesc_type0 { 722 uint32_t sf_addrlo; 723 #define SF_RX_DESC_VALID 0x00000001 724 #define SF_RX_DESC_END 0x00000002 725 }; 726 727 /* 728 * RX buffer descriptor type 1, 64-bit addressing. 729 */ 730 struct sf_rx_bufdesc_type1 { 731 uint64_t sf_addr; 732 }; 733 734 /* 735 * RX completion descriptor, type 0 (short). 736 */ 737 struct sf_rx_cmpdesc_type0 { 738 uint32_t sf_rx_status1; 739 #define SF_RX_CMPDESC_LEN 0x0000ffff 740 #define SF_RX_CMPDESC_EIDX 0x07ff0000 741 #define SF_RX_CMPDESC_STAT1 0x38000000 742 #define SF_RX_CMPDESC_ID 0x40000000 743 }; 744 745 /* 746 * RX completion descriptor, type 1 (basic). Includes vlan ID 747 * if this is a vlan-addressed packet, plus extended status. 748 */ 749 struct sf_rx_cmpdesc_type1 { 750 uint32_t sf_rx_status1; 751 uint32_t sf_rx_status2; 752 #define SF_RX_CMPDESC_VLAN 0x0000ffff 753 #define SF_RX_CMPDESC_STAT2 0xffff0000 754 }; 755 756 /* 757 * RX completion descriptor, type 2 (checksum). Includes partial TCP/IP 758 * checksum instead of vlan tag, plus extended status. 759 */ 760 struct sf_rx_cmpdesc_type2 { 761 uint32_t sf_rx_status1; 762 uint32_t sf_rx_status2; 763 #define SF_RX_CMPDESC_CSUM2 0x0000ffff 764 }; 765 766 /* 767 * RX completion descriptor type 3 (full). Includes timestamp, partial 768 * TCP/IP checksum, vlan tag plus priority, two extended status fields. 769 */ 770 struct sf_rx_cmpdesc_type3 { 771 uint32_t sf_rx_status1; 772 uint32_t sf_rx_status2; 773 uint32_t sf_rx_status3; 774 #define SF_RX_CMPDESC_CSUM3 0xffff0000 775 #define SF_RX_CMPDESC_VLANPRI 0x0000ffff 776 uint32_t sf_rx_timestamp; 777 }; 778 779 #define SF_RXSTAT1_QUEUE 0x08000000 780 #define SF_RXSTAT1_FIFOFULL 0x10000000 781 #define SF_RXSTAT1_OK 0x20000000 782 783 #define SF_RXSTAT2_FRAMETYPE_MASK 0x00070000 784 #define SF_RXSTAT2_FRAMETYPE_UNKN 0x00000000 785 #define SF_RXSTAT2_FRAMETYPE_IPV4 0x00010000 786 #define SF_RXSTAT2_FRAMETYPE_IPV6 0x00020000 787 #define SF_RXSTAT2_FRAMETYPE_IPX 0x00030000 788 #define SF_RXSTAT2_FRAMETYPE_ICMP 0x00040000 789 #define SF_RXSTAT2_FRAMETYPE_UNSPRT 0x00050000 790 #define SF_RXSTAT2_UDP 0x00080000 791 #define SF_RXSTAT2_TCP 0x00100000 792 #define SF_RXSTAT2_FRAG 0x00200000 793 #define SF_RXSTAT2_PCSUM_OK 0x00400000 /* partial checksum ok */ 794 #define SF_RXSTAT2_CSUM_BAD 0x00800000 /* TCP/IP checksum bad */ 795 #define SF_RXSTAT2_CSUM_OK 0x01000000 /* TCP/IP checksum ok */ 796 #define SF_RXSTAT2_VLAN 0x02000000 797 #define SF_RXSTAT2_BADRXCODE 0x04000000 798 #define SF_RXSTAT2_DRIBBLE 0x08000000 799 #define SF_RXSTAT2_ISL_CRCERR 0x10000000 800 #define SF_RXSTAT2_CRCERR 0x20000000 801 #define SF_RXSTAT2_HASH 0x40000000 802 #define SF_RXSTAT2_PERFECT 0x80000000 803 #define SF_RXSTAT2_MASK 0xFFFF0000 804 805 #define SF_RXSTAT3_ISL 0x00008000 806 #define SF_RXSTAT3_PAUSE 0x00004000 807 #define SF_RXSTAT3_CONTROL 0x00002000 808 #define SF_RXSTAT3_HEADER 0x00001000 809 #define SF_RXSTAT3_TRAILER 0x00000800 810 #define SF_RXSTAT3_START_IDX_MASK 0x000007FF 811 812 struct sf_frag { 813 uint32_t sf_addr; 814 uint16_t sf_fraglen; 815 uint16_t sf_pktlen; 816 }; 817 818 struct sf_frag_msdos { 819 uint16_t sf_pktlen; 820 uint16_t sf_fraglen; 821 uint32_t sf_addr; 822 }; 823 824 /* 825 * TX frame descriptor type 0, 32-bit addressing. One descriptor can 826 * be used to map multiple packet fragments. Note that the number of 827 * fragments can be variable depending on how the descriptor spacing 828 * is specified in the TX descriptor queue control register. 829 * We always use a spacing of 128 bytes, and a skipfield length of 8 830 * bytes: this means 16 bytes for the descriptor, including the skipfield, 831 * with 121 bytes left for fragment maps. Each fragment requires 8 bytes, 832 * which allows for 14 fragments per descriptor. The total size of the 833 * transmit buffer queue is limited to 16384 bytes, so with a spacing of 834 * 128 bytes per descriptor, we have room for 128 descriptors in the queue. 835 */ 836 struct sf_tx_bufdesc_type0 { 837 uint32_t sf_tx_ctrl; 838 #define SF_TX_DESC_CRCEN 0x01000000 839 #define SF_TX_DESC_CALTCP 0x02000000 840 #define SF_TX_DESC_END 0x04000000 841 #define SF_TX_DESC_INTR 0x08000000 842 #define SF_TX_DESC_ID 0xb0000000 843 uint32_t sf_tx_frag; 844 /* 845 * Depending on descriptor spacing/skip field length it 846 * can have fixed number of struct sf_frag. 847 * struct sf_frag sf_frags[14]; 848 */ 849 }; 850 851 /* 852 * TX buffer descriptor type 1, 32-bit addressing. Each descriptor 853 * maps a single fragment. 854 */ 855 struct sf_tx_bufdesc_type1 { 856 uint32_t sf_tx_ctrl; 857 #define SF_TX_DESC_FRAGLEN 0x0000ffff 858 #define SF_TX_DESC_FRAGCNT 0x00ff0000 859 uint32_t sf_addrlo; 860 }; 861 862 /* 863 * TX buffer descriptor type 2, 64-bit addressing. Each descriptor 864 * maps a single fragment. 865 */ 866 struct sf_tx_bufdesc_type2 { 867 uint32_t sf_tx_ctrl; 868 uint32_t sf_tx_reserved; 869 uint64_t sf_addr; 870 }; 871 872 /* TX buffer descriptor type 3 is not defined. */ 873 874 /* 875 * TX frame descriptor type 4, 32-bit addressing. This is a special 876 * case of the type 0 descriptor, identical except that the fragment 877 * address and length fields are ordered differently. This is done 878 * to optimize copies in MS-DOS and OS/2 drivers. 879 */ 880 struct sf_tx_bufdesc_type4 { 881 uint32_t sf_tx_ctrl; 882 uint32_t sf_tx_frag; 883 /* 884 * Depending on descriptor spacing/skip field length it 885 * can have fixed number of struct sf_frag_msdos. 886 * 887 * struct sf_frag_msdos sf_frags[14]; 888 */ 889 }; 890 891 /* 892 * Transmit completion queue descriptor formats. 893 */ 894 895 /* 896 * Transmit DMA completion descriptor, type 0. 897 */ 898 #define SF_TXCMPTYPE_DMA 0x80000000 899 #define SF_TXCMPTYPE_TX 0xa0000000 900 struct sf_tx_cmpdesc_type0 { 901 uint32_t sf_tx_status1; 902 #define SF_TX_CMPDESC_IDX 0x00007fff 903 #define SF_TX_CMPDESC_HIPRI 0x00008000 904 #define SF_TX_CMPDESC_STAT 0x1fff0000 905 #define SF_TX_CMPDESC_TYPE 0xe0000000 906 }; 907 908 /* 909 * Transmit completion descriptor, type 1. 910 */ 911 struct sf_tx_cmpdesc_type1 { 912 uint32_t sf_tx_status1; 913 uint32_t sf_tx_status2; 914 }; 915 916 #define SF_TXSTAT_CRCERR 0x00010000 917 #define SF_TXSTAT_LENCHECKERR 0x00020000 918 #define SF_TXSTAT_LENRANGEERR 0x00040000 919 #define SF_TXSTAT_TX_OK 0x00080000 920 #define SF_TXSTAT_TX_DEFERED 0x00100000 921 #define SF_TXSTAT_EXCESS_DEFER 0x00200000 922 #define SF_TXSTAT_EXCESS_COLL 0x00400000 923 #define SF_TXSTAT_LATE_COLL 0x00800000 924 #define SF_TXSTAT_TOOBIG 0x01000000 925 #define SF_TXSTAT_TX_UNDERRUN 0x02000000 926 #define SF_TXSTAT_CTLFRAME_OK 0x04000000 927 #define SF_TXSTAT_PAUSEFRAME_OK 0x08000000 928 #define SF_TXSTAT_PAUSED 0x10000000 929 930 /* Statistics counters. */ 931 struct sf_stats { 932 uint64_t sf_tx_frames; 933 uint32_t sf_tx_single_colls; 934 uint32_t sf_tx_multi_colls; 935 uint32_t sf_tx_crcerrs; 936 uint64_t sf_tx_bytes; 937 uint32_t sf_tx_deferred; 938 uint32_t sf_tx_late_colls; 939 uint32_t sf_tx_pause_frames; 940 uint32_t sf_tx_control_frames; 941 uint32_t sf_tx_excess_colls; 942 uint32_t sf_tx_excess_defer; 943 uint32_t sf_tx_mcast_frames; 944 uint32_t sf_tx_bcast_frames; 945 uint32_t sf_tx_frames_lost; 946 uint64_t sf_rx_frames; 947 uint32_t sf_rx_crcerrs; 948 uint32_t sf_rx_alignerrs; 949 uint64_t sf_rx_bytes; 950 uint32_t sf_rx_pause_frames; 951 uint32_t sf_rx_control_frames; 952 uint32_t sf_rx_unsup_control_frames; 953 uint32_t sf_rx_giants; 954 uint32_t sf_rx_runts; 955 uint32_t sf_rx_jabbererrs; 956 uint32_t sf_rx_fragments; 957 uint64_t sf_rx_pkts_64; 958 uint64_t sf_rx_pkts_65_127; 959 uint64_t sf_rx_pkts_128_255; 960 uint64_t sf_rx_pkts_256_511; 961 uint64_t sf_rx_pkts_512_1023; 962 uint64_t sf_rx_pkts_1024_1518; 963 uint32_t sf_rx_frames_lost; 964 uint32_t sf_tx_underruns; 965 uint32_t sf_tx_gfp_stall; 966 uint32_t sf_rx_gfp_stall; 967 }; 968 969 /* 970 * register space access macros 971 */ 972 #define CSR_WRITE_4(sc, reg, val) \ 973 bus_write_4((sc)->sf_res, reg, val) 974 975 #define CSR_READ_4(sc, reg) \ 976 bus_read_4((sc)->sf_res, reg) 977 978 #define CSR_READ_1(sc, reg) \ 979 bus_read_1((sc)->sf_res, reg) 980 981 982 struct sf_type { 983 uint16_t sf_vid; 984 uint16_t sf_did; 985 char *sf_name; 986 uint16_t sf_sdid; 987 char *sf_sname; 988 }; 989 990 /* Use Tx descriptor type 2 : 64bit buffer descriptor */ 991 #define sf_tx_rdesc sf_tx_bufdesc_type2 992 /* Use Rx descriptor type 1 : 64bit buffer descriptor */ 993 #define sf_rx_rdesc sf_rx_bufdesc_type1 994 /* Use Tx completion type 0 */ 995 #define sf_tx_rcdesc sf_tx_cmpdesc_type0 996 /* Use Rx completion type 2 : checksum */ 997 #define sf_rx_rcdesc sf_rx_cmpdesc_type2 998 999 #define SF_TX_DLIST_CNT 256 1000 #define SF_RX_DLIST_CNT 256 1001 #define SF_TX_CLIST_CNT 1024 1002 #define SF_RX_CLIST_CNT 1024 1003 #define SF_TX_DLIST_SIZE (sizeof(struct sf_tx_rdesc) * SF_TX_DLIST_CNT) 1004 #define SF_TX_CLIST_SIZE (sizeof(struct sf_tx_rcdesc) * SF_TX_CLIST_CNT) 1005 #define SF_RX_DLIST_SIZE (sizeof(struct sf_rx_rdesc) * SF_RX_DLIST_CNT) 1006 #define SF_RX_CLIST_SIZE (sizeof(struct sf_rx_rcdesc) * SF_RX_CLIST_CNT) 1007 #define SF_RING_ALIGN 256 1008 #define SF_RX_ALIGN sizeof(uint32_t) 1009 #define SF_MAXTXSEGS 16 1010 1011 #define SF_ADDR_LO(x) ((uint64_t)(x) & 0xffffffff) 1012 #define SF_ADDR_HI(x) ((uint64_t)(x) >> 32) 1013 #define SF_TX_DLIST_ADDR(sc, i) \ 1014 ((sc)->sf_rdata.sf_tx_ring_paddr + sizeof(struct sf_tx_rdesc) * (i)) 1015 #define SF_TX_CLIST_ADDR(sc, i) \ 1016 ((sc)->sf_rdata.sf_tx_cring_paddr + sizeof(struct sf_tx_crdesc) * (i)) 1017 #define SF_RX_DLIST_ADDR(sc, i) \ 1018 ((sc)->sf_rdata.sf_rx_ring_paddr + sizeof(struct sf_rx_rdesc) * (i)) 1019 #define SF_RX_CLIST_ADDR(sc, i) \ 1020 ((sc)->sf_rdata.sf_rx_cring_paddr + sizeof(struct sf_rx_rcdesc) * (i)) 1021 1022 #define SF_INC(x, y) (x) = ((x) + 1) % y 1023 1024 #define SF_MAX_FRAMELEN 1536 1025 #define SF_TX_THRESHOLD_UNIT 16 1026 #define SF_MAX_TX_THRESHOLD (SF_MAX_FRAMELEN / SF_TX_THRESHOLD_UNIT) 1027 #define SF_MIN_TX_THRESHOLD (128 / SF_TX_THRESHOLD_UNIT) 1028 1029 struct sf_txdesc { 1030 struct mbuf *tx_m; 1031 int ndesc; 1032 bus_dmamap_t tx_dmamap; 1033 }; 1034 1035 struct sf_rxdesc { 1036 struct mbuf *rx_m; 1037 bus_dmamap_t rx_dmamap; 1038 }; 1039 1040 struct sf_chain_data { 1041 bus_dma_tag_t sf_parent_tag; 1042 bus_dma_tag_t sf_tx_tag; 1043 struct sf_txdesc sf_txdesc[SF_TX_DLIST_CNT]; 1044 bus_dma_tag_t sf_rx_tag; 1045 struct sf_rxdesc sf_rxdesc[SF_RX_DLIST_CNT]; 1046 bus_dma_tag_t sf_tx_ring_tag; 1047 bus_dma_tag_t sf_rx_ring_tag; 1048 bus_dma_tag_t sf_tx_cring_tag; 1049 bus_dma_tag_t sf_rx_cring_tag; 1050 bus_dmamap_t sf_tx_ring_map; 1051 bus_dmamap_t sf_rx_ring_map; 1052 bus_dmamap_t sf_rx_sparemap; 1053 bus_dmamap_t sf_tx_cring_map; 1054 bus_dmamap_t sf_rx_cring_map; 1055 int sf_tx_prod; 1056 int sf_tx_cnt; 1057 int sf_txc_cons; 1058 int sf_rxc_cons; 1059 }; 1060 1061 struct sf_ring_data { 1062 struct sf_tx_rdesc *sf_tx_ring; 1063 bus_addr_t sf_tx_ring_paddr; 1064 struct sf_tx_rcdesc *sf_tx_cring; 1065 bus_addr_t sf_tx_cring_paddr; 1066 struct sf_rx_rdesc *sf_rx_ring; 1067 bus_addr_t sf_rx_ring_paddr; 1068 struct sf_rx_rcdesc *sf_rx_cring; 1069 bus_addr_t sf_rx_cring_paddr; 1070 }; 1071 1072 1073 struct sf_softc { 1074 struct ifnet *sf_ifp; /* interface info */ 1075 device_t sf_dev; /* device info */ 1076 void *sf_intrhand; /* interrupt handler cookie */ 1077 struct resource *sf_irq; /* irq resource descriptor */ 1078 struct resource *sf_res; /* mem/ioport resource */ 1079 int sf_restype; 1080 int sf_rid; 1081 struct sf_type *sf_info; /* Starfire adapter info */ 1082 device_t sf_miibus; 1083 struct sf_chain_data sf_cdata; 1084 struct sf_ring_data sf_rdata; 1085 int sf_if_flags; 1086 struct callout sf_co; 1087 int sf_watchdog_timer; 1088 int sf_link; 1089 int sf_suspended; 1090 int sf_detach; 1091 uint32_t sf_txthresh; 1092 int sf_int_mod; 1093 struct sf_stats sf_statistics; 1094 struct mtx sf_mtx; 1095 #ifdef DEVICE_POLLING 1096 int rxcycles; 1097 #endif /* DEVICE_POLLING */ 1098 }; 1099 1100 1101 #define SF_LOCK(_sc) mtx_lock(&(_sc)->sf_mtx) 1102 #define SF_UNLOCK(_sc) mtx_unlock(&(_sc)->sf_mtx) 1103 #define SF_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sf_mtx, MA_OWNED) 1104 1105 #define SF_TIMEOUT 1000 1106