Home
last modified time | relevance | path

Searched refs:RegisterClasses (Results 1 – 4 of 4) sorted by relevance

/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp137 if (!RegisterClasses.empty()) { in runEnums()
140 assert(RegisterClasses.size() <= 0xffff && in runEnums()
147 for (const auto &RC : RegisterClasses) in runEnums()
1038 for (const auto &RC : RegisterClasses) { in runMCDesc()
1076 for (const auto &RC : RegisterClasses) { in runMCDesc()
1181 if (!RegisterClasses.empty()) { in runTargetHeader()
1185 for (const auto &RC : RegisterClasses) { in runTargetHeader()
1222 for (const auto &RC : RegisterClasses) { in runTargetDesc()
1268 if (!RegisterClasses.empty()) { in runTargetDesc()
1428 for (const auto &RC : RegisterClasses) in runTargetDesc()
[all …]
H A DAsmMatcherEmitter.cpp731 RegisterClassesTy RegisterClasses; member in __anon3c98f17f0111::AsmMatcherInfo
1327 RegisterClasses[it->first] = RegisterSetClasses[it->second]; in buildRegisterClasses()
1331 ClassInfo *CI = RegisterClasses[Rec]; in buildRegisterClasses()
1578 Op.Class = RegisterClasses[RegRecord]; in buildInfo()
2490 for (const auto &RC : Info.RegisterClasses) in emitValidateOperandClass()
H A DCodeGenSchedule.cpp1804 RecVec RegisterClasses = RF->getValueAsListOfDefs("RegClasses"); in collectRegisterFiles() local
1807 for (unsigned I = 0, E = RegisterClasses.size(); I < E; ++I) { in collectRegisterFiles()
1816 CGRF.Costs.emplace_back(RegisterClasses[I], Cost, AllowMoveElim); in collectRegisterFiles()
/freebsd-12.1/contrib/llvm/include/llvm/Target/GlobalISel/
H A DRegisterBank.td15 list<RegisterClass> RegisterClasses = classes;