| /freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/ |
| H A D | RegisterBank.cpp | 21 const unsigned RegisterBank::InvalidID = UINT_MAX;
23 RegisterBank::RegisterBank( in RegisterBank() function in RegisterBank
31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const { in verify()
60 bool RegisterBank::covers(const TargetRegisterClass &RC) const { in covers()
65 bool RegisterBank::isValid() const { in isValid()
71 bool RegisterBank::operator==(const RegisterBank &OtherRB) const { in operator ==()
81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const { in dump()
86 void RegisterBank::print(raw_ostream &OS, bool IsForDebug, in print()
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| H A D | RegisterBankInfo.cpp | 59 RegisterBankInfo::RegisterBankInfo(RegisterBank **RegBanks, in RegisterBankInfo()
73 const RegisterBank &RegBank = getRegBank(Idx); in verify()
83 const RegisterBank *
91 if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>()) in getRegBank()
111 const RegisterBank *RegisterBankInfo::getRegBankFromConstraints( in getRegBankFromConstraints()
121 const RegisterBank &RegBank = getRegBankFromRegClass(*RC); in getRegBankFromConstraints()
136 const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>(); in constrainGenericRegister()
192 const RegisterBank *AltRegBank = getRegBank(Reg, MRI, TRI); in getInstrMappingImpl()
196 const RegisterBank *CurRegBank = IsCopyLike ? AltRegBank : nullptr; in getInstrMappingImpl()
234 const RegisterBank *RegBank) { in hashPartialMapping()
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| H A D | RegBankSelect.cpp | 122 const RegisterBank *CurRegBank = RBI->getRegBank(Reg, *MRI, *TRI); in assignmentMatch()
123 const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank; in assignmentMatch()
195 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI); in getRepairCost()
210 const RegisterBank *DesiredRegBrank = ValMapping.BreakDown[0].RegBank; in getRepairCost()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | RegisterBankInfo.h | 32 class RegisterBank; variable
59 const RegisterBank *RegBank;
65 const RegisterBank &RegBank) in PartialMapping()
386 RegisterBank **RegBanks;
417 RegisterBankInfo(RegisterBank **RegBanks, unsigned NumRegBanks);
430 RegisterBank &getRegBank(unsigned ID) { in getRegBank()
470 const RegisterBank &RegBank) const;
543 const RegisterBank *
574 const RegisterBank &getRegBank(unsigned ID) const { in getRegBank()
601 virtual const RegisterBank &
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| H A D | RegisterBank.h | 29 class RegisterBank {
44 RegisterBank(unsigned ID, const char *Name, unsigned Size,
75 bool operator==(const RegisterBank &OtherRB) const;
76 bool operator!=(const RegisterBank &OtherRB) const {
93 inline raw_ostream &operator<<(raw_ostream &OS, const RegisterBank &RegBank) {
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| H A D | CSEInfo.h | 160 class RegisterBank; variable
177 const GISelInstProfileBuilder &addNodeIDRegType(const RegisterBank *RB) const;
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | RegisterBankEmitter.cpp | 29 class RegisterBank { class
44 RegisterBank(const Record &TheDef) in RegisterBank() function in __anon7080cf5b0111::RegisterBank
112 const std::vector<RegisterBank> &Banks);
114 const std::vector<RegisterBank> &Banks);
116 std::vector<RegisterBank> &Banks);
131 const std::vector<RegisterBank> &Banks) { in emitHeader()
147 const std::vector<RegisterBank> &Banks) { in emitBaseClassDefinition()
215 std::vector<RegisterBank> &Banks) { in emitBaseClassImplementation()
284 std::vector<RegisterBank> Banks; in run()
287 RegisterBank Bank(*V); in run()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBanks.td | 10 def SGPRRegBank : RegisterBank<"SGPR",
14 def VGPRRegBank : RegisterBank<"VGPR",
18 def SCCRegBank : RegisterBank <"SCC", [SCC_CLASS]>;
21 def VCCRegBank : RegisterBank <"VCC", [SReg_64]>;
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| H A D | AMDGPURegisterBankInfo.h | 57 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
60 const RegisterBank &
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| H A D | AMDGPURegisterBankInfo.cpp | 45 const RegisterBank &RBSGPR = getRegBank(AMDGPU::SGPRRegBankID); in AMDGPURegisterBankInfo()
49 const RegisterBank &RBVGPR = getRegBank(AMDGPU::VGPRRegBankID); in AMDGPURegisterBankInfo()
73 unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst, in copyCost()
74 const RegisterBank &Src, in copyCost()
92 const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass( in getRegBankFromRegClass()
263 if (const RegisterBank *Bank = getRegBank(Reg, MRI, *TRI)) { in isSALUMapping()
374 const RegisterBank *Bank = getRegBank(Reg, MRI, TRI); in getRegBankID()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64RegisterBankInfo.h | 64 unsigned ValLength, const RegisterBank &RB);
120 unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
123 const RegisterBank &
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| H A D | AArch64RegisterBanks.td | 14 def GPRRegBank : RegisterBank<"GPR", [GPR64all]>;
17 def FPRRegBank : RegisterBank<"FPR", [QQQQ]>;
20 def CCRegBank : RegisterBank<"CC", [CCR]>;
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| H A D | AArch64RegisterBankInfo.cpp | 52 const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID); in AArch64RegisterBankInfo()
57 const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID); in AArch64RegisterBankInfo()
62 const RegisterBank &RBCCR = getRegBank(AArch64::CCRegBankID); in AArch64RegisterBankInfo()
205 unsigned AArch64RegisterBankInfo::copyCost(const RegisterBank &A, in copyCost()
206 const RegisterBank &B, in copyCost()
226 const RegisterBank &AArch64RegisterBankInfo::getRegBankFromRegClass( in getRegBankFromRegClass()
499 const RegisterBank *DstRB = getRegBank(DstReg, MRI, TRI); in getInstrMapping()
500 const RegisterBank *SrcRB = getRegBank(SrcReg, MRI, TRI); in getInstrMapping()
524 const RegisterBank &DstRB = in getInstrMapping()
526 const RegisterBank &SrcRB = in getInstrMapping()
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| H A D | AArch64InstructionSelector.cpp | 152 getRegClassForTypeOnBank(LLT Ty, const RegisterBank &RB, in getRegClassForTypeOnBank()
196 const RegisterBank *PrevOpBank = nullptr; in unsupportedBinOp()
404 const RegisterBank *RB = nullptr; in selectCopy()
406 RB = RegClassOrBank.get<const RegisterBank *>(); in selectCopy()
615 const RegisterBank &RB = *RBI.getRegBank(LHS, MRI, TRI); in selectCompareBranch()
746 const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>(); in select()
840 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
1057 const RegisterBank &RB = *RBI.getRegBank(ValReg, MRI, TRI); in select()
1111 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
1149 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in select()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIParser.h | 26 class RegisterBank; variable
40 const RegisterBank *RegBank;
47 using Name2RegBankMap = StringMap<const RegisterBank *>;
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/GlobalISel/ |
| H A D | RegisterBank.td | 1 //===- RegisterBank.td - Register bank definitions ---------*- tablegen -*-===//
13 class RegisterBank<string name, list<RegisterClass> classes> {
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMRegisterBanks.td | 13 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
14 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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| H A D | ARMRegisterBankInfo.h | 36 const RegisterBank &
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86RegisterBanks.td | 14 def GPRRegBank : RegisterBank<"GPR", [GR64]>;
17 def VECRRegBank : RegisterBank<"VECR", [VR512]>;
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| H A D | X86InstructionSelector.cpp | 203 const RegisterBank &RegBank = *RBI.getRegBank(Reg, MRI, TRI); in getRegClass()
514 const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); in selectLoadStoreOp()
711 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectTruncOrPtrToInt()
712 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectTruncOrPtrToInt()
800 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectZext()
801 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectZext()
886 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectAnyext()
887 const RegisterBank &SrcRB = *RBI.getRegBank(SrcReg, MRI, TRI); in selectAnyext()
1365 const RegisterBank &RegBank = *RBI.getRegBank(DstReg, MRI, TRI); in selectMergeValues()
1529 const RegisterBank &DstRB = *RBI.getRegBank(DstReg, MRI, TRI); in selectShift()
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| H A D | X86RegisterBankInfo.h | 68 const RegisterBank &
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| H A D | X86RegisterBankInfo.cpp | 33 const RegisterBank &RBGPR = getRegBank(X86::GPRRegBankID); in X86RegisterBankInfo()
44 const RegisterBank &X86RegisterBankInfo::getRegBankFromRegClass( in getRegBankFromRegClass()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsRegisterBanks.td | 13 def GPRBRegBank : RegisterBank<"GPRB", [GPR32]>;
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| H A D | MipsRegisterBankInfo.h | 36 const RegisterBank &
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 48 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
653 const RegisterBank *getRegBankOrNull(unsigned Reg) const { in getRegBankOrNull()
655 return Val.dyn_cast<const RegisterBank *>(); in getRegBankOrNull()
669 void setRegBank(unsigned Reg, const RegisterBank &RegBank);
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