| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | RegisterPressure.cpp | 348 unsigned RegUnit = Pair.RegUnit; in initLiveThru() local
359 return Other.RegUnit == RegUnit; in getRegLanes()
368 unsigned RegUnit = Pair.RegUnit; in addRegLanes() local
371 return Other.RegUnit == RegUnit; in addRegLanes()
383 return Other.RegUnit == RegUnit; in setRegZero()
394 unsigned RegUnit = Pair.RegUnit; in removeRegLanes() local
397 return Other.RegUnit == RegUnit; in removeRegLanes()
593 unsigned RegUnit = I->RegUnit; in adjustLaneLiveness() local
619 unsigned RegUnit = P.RegUnit; in adjustLaneLiveness() local
702 unsigned RegUnit = Pair.RegUnit; in discoverLiveInOrOut() local
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| H A D | LiveRegMatrix.cpp | 179 unsigned RegUnit) { in query() argument
180 LiveIntervalUnion::Query &Q = Queries[RegUnit]; in query()
181 Q.init(UserTag, LR, Matrix[RegUnit]); in query()
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| H A D | MachineCopyPropagation.cpp | 144 MachineInstr *findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI, in findCopyForUnit() argument
146 auto CI = Copies.find(RegUnit); in findCopyForUnit()
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| H A D | MachineTraceMetrics.cpp | 1144 TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle)); in computeInstrHeights()
1145 LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@' in computeInstrHeights()
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| H A D | MachineScheduler.cpp | 1112 unsigned Reg = P.RegUnit; in updatePressureDiffs()
1339 unsigned Reg = P.RegUnit; in computeCyclicCriticalPath()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | RegisterPressure.h | 41 unsigned RegUnit; ///< Virtual register or register unit. member
44 RegisterMaskPair(unsigned RegUnit, LaneBitmask LaneMask) in RegisterMaskPair()
45 : RegUnit(RegUnit), LaneMask(LaneMask) {} in RegisterMaskPair()
163 void addPressureChange(unsigned RegUnit, bool IsDec,
308 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
321 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
553 void increaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
555 void decreaseRegPressure(unsigned RegUnit, LaneBitmask PreviousMask,
566 LaneBitmask getLastUsedLanes(unsigned RegUnit, SlotIndex Pos) const;
567 LaneBitmask getLiveLanesAt(unsigned RegUnit, SlotIndex Pos) const;
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| H A D | MachineRegisterInfo.h | 618 PSetIterator getPressureSets(unsigned RegUnit) const;
1161 PSetIterator(unsigned RegUnit, const MachineRegisterInfo *MRI) { in PSetIterator() argument
1163 if (TargetRegisterInfo::isVirtualRegister(RegUnit)) { in PSetIterator()
1164 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit); in PSetIterator()
1169 PSet = TRI->getRegUnitPressureSets(RegUnit); in PSetIterator()
1170 Weight = TRI->getRegUnitWeight(RegUnit); in PSetIterator()
1191 getPressureSets(unsigned RegUnit) const { in getPressureSets() argument
1192 return PSetIterator(RegUnit, this); in getPressureSets()
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| H A D | MachineTraceMetrics.h | 77 unsigned RegUnit; member
82 unsigned getSparseSetIndex() const { return RegUnit; } in getSparseSetIndex()
84 LiveRegUnit(unsigned RU) : RegUnit(RU) {} in LiveRegUnit()
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| H A D | TargetRegisterInfo.h | 440 bool hasRegUnit(unsigned Reg, unsigned RegUnit) const { in hasRegUnit() argument
442 if (*Units == RegUnit) in hasRegUnit()
773 virtual unsigned getRegUnitWeight(unsigned RegUnit) const = 0;
793 virtual const int *getRegUnitPressureSets(unsigned RegUnit) const = 0;
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| H A D | LiveRegMatrix.h | 151 LiveIntervalUnion::Query &query(const LiveRange &LR, unsigned RegUnit);
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 472 struct RegUnit { struct
490 RegUnit() : Weight(0), RegClassUnitSetsIdx(0), Artificial(false) { in RegUnit() argument
541 SmallVector<RegUnit, 8> RegUnits;
665 RegUnit &RU = RegUnits.back();
693 RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } in getRegUnit()
694 const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } in getRegUnit()
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| H A D | RegisterInfoEmitter.cpp | 237 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); in EmitRegUnitPressure()
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| H A D | CodeGenRegisters.cpp | 1073 const RegUnit &RU = RegBank.getRegUnit(*UnitI); in buildRegUnitSet()
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| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 642 MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) { in MCRegUnitRootIterator() argument
643 assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit"); in MCRegUnitRootIterator()
644 Reg0 = MCRI->RegUnitRoots[RegUnit][0]; in MCRegUnitRootIterator()
645 Reg1 = MCRI->RegUnitRoots[RegUnit][1]; in MCRegUnitRootIterator()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | GCNRegPressure.cpp | 240 return RM.RegUnit == Reg; in collectVirtualRegUses()
321 auto LiveMask = LiveRegs[U.RegUnit]; in recede()
322 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI); in recede()
344 auto &LiveMask = LiveRegs[U.RegUnit]; in recede()
347 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI); in recede()
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| H A D | SIWholeQuadMode.cpp | 283 for (MCRegUnitIterator RegUnit(Reg, TRI); RegUnit.isValid(); ++RegUnit) { in markInstructionUses() local
284 LiveRange &LR = LIS->getRegUnit(*RegUnit); in markInstructionUses()
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| H A D | SIMachineScheduler.h | 476 InRegs.insert(RegMaskPair.RegUnit); in getInRegs()
484 OutRegs.insert(RegMaskPair.RegUnit); in getOutRegs()
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| H A D | SIRegisterInfo.h | 223 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
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| H A D | SIRegisterInfo.cpp | 1567 const int *SIRegisterInfo::getRegUnitPressureSets(unsigned RegUnit) const { in getRegUnitPressureSets()
1570 if (hasRegUnit(AMDGPU::M0, RegUnit)) in getRegUnitPressureSets()
1572 return AMDGPURegisterInfo::getRegUnitPressureSets(RegUnit); in getRegUnitPressureSets()
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| H A D | SIMachineScheduler.cpp | 352 if (TargetRegisterInfo::isVirtualRegister(RegMaskPair.RegUnit)) in initRegPressure()
353 LiveInRegs.insert(RegMaskPair.RegUnit); in initRegPressure()
379 unsigned Reg = RegMaskPair.RegUnit; in initRegPressure()
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