| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMCallingConv.h | 34 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
49 if (unsigned Reg = State.AllocateReg(RegList)) in f64AssignAPCS()
206 ArrayRef<MCPhysReg> RegList; in CC_ARM_AAPCS_Custom_Aggregate() local
209 RegList = RRegList; in CC_ARM_AAPCS_Custom_Aggregate()
216 State.AllocateReg(RegList[RegIdx++]); in CC_ARM_AAPCS_Custom_Aggregate()
222 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
226 RegList = DRegList; in CC_ARM_AAPCS_Custom_Aggregate()
230 RegList = QRegList; in CC_ARM_AAPCS_Custom_Aggregate()
256 if (RegIdx >= RegList.size()) in CC_ARM_AAPCS_Custom_Aggregate()
266 RegList = SRegList; in CC_ARM_AAPCS_Custom_Aggregate()
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| H A D | ARMAsmPrinter.cpp | 1101 SmallVector<unsigned, 4> RegList; in EmitUnwindingInstruction() local
1134 assert(RegList.empty() && in EmitUnwindingInstruction()
1141 RegList.push_back(MO.getReg()); in EmitUnwindingInstruction()
1149 RegList.push_back(SrcReg); in EmitUnwindingInstruction()
1153 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD); in EmitUnwindingInstruction()
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| H A D | ARMBaseRegisterInfo.cpp | 69 const MCPhysReg *RegList = in getCalleeSavedRegs() local
108 return RegList; in getCalleeSavedRegs()
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| H A D | ARMBaseInstrInfo.cpp | 2314 SmallVector<MachineOperand, 4> RegList; in tryFoldSPUpdateIntoPushPop() local
2323 RegList.push_back(MO); in tryFoldSPUpdateIntoPushPop()
2339 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false, in tryFoldSPUpdateIntoPushPop()
2361 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false, in tryFoldSPUpdateIntoPushPop()
2377 for (int i = RegList.size() - 1; i >= 0; --i) in tryFoldSPUpdateIntoPushPop()
2378 MIB.add(RegList[i]); in tryFoldSPUpdateIntoPushPop()
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| H A D | ARMInstrInfo.td | 547 def RegListAsmOperand : AsmOperandClass { let Name = "RegList"; }
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | CallingConvEmitter.cpp | 113 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
114 if (RegList->size() == 1) { in EmitAction()
116 O << getQualifiedName(RegList->getElementAsRecord(0)) << ")) {\n"; in EmitAction()
121 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
123 O << getQualifiedName(RegList->getElementAsRecord(i)); in EmitAction()
134 ListInit *RegList = Action->getValueAsListInit("RegList"); in EmitAction() local
136 if (!ShadowRegList->empty() && ShadowRegList->size() != RegList->size()) in EmitAction()
139 if (RegList->size() == 1) { in EmitAction()
141 O << getQualifiedName(RegList->getElementAsRecord(0)); in EmitAction()
151 for (unsigned i = 0, e = RegList->size(); i != e; ++i) { in EmitAction()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64CallingConvention.h | 89 ArrayRef<MCPhysReg> RegList; in CC_AArch64_Custom_Block() local
91 RegList = XRegList; in CC_AArch64_Custom_Block()
93 RegList = HRegList; in CC_AArch64_Custom_Block()
95 RegList = SRegList; in CC_AArch64_Custom_Block()
97 RegList = DRegList; in CC_AArch64_Custom_Block()
99 RegList = QRegList; in CC_AArch64_Custom_Block()
115 unsigned RegResult = State.AllocateRegBlock(RegList, PendingMembers.size()); in CC_AArch64_Custom_Block()
127 for (auto Reg : RegList) in CC_AArch64_Custom_Block()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86CallingConv.h | 67 static const MCPhysReg RegList[] = {X86::EAX, X86::EDX, X86::ECX}; in CC_X86_32_MCUInReg() local
68 static const unsigned NumRegs = sizeof(RegList)/sizeof(RegList[0]); in CC_X86_32_MCUInReg()
86 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_X86_32_MCUInReg()
102 unsigned FirstFree = State.getFirstUnallocated(RegList); in CC_X86_32_MCUInReg()
107 It.convertToReg(State.AllocateReg(RegList[FirstFree++])); in CC_X86_32_MCUInReg()
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| H A D | X86CallingConv.cpp | 27 static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI, in CC_X86_32_RegCall_Assign2Regs() local
34 for (auto Reg : RegList) { in CC_X86_32_RegCall_Assign2Regs()
90 ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT); in CC_X86_VectorCallAssignRegister() local
95 for (auto Reg : RegList) { in CC_X86_VectorCallAssignRegister()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMELFStreamer.cpp | 86 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
160 assert(RegList.size() && "RegList should not be empty"); in emitRegSave()
166 InstPrinter.printRegName(OS, RegList[0]); in emitRegSave()
168 for (unsigned i = 1, e = RegList.size(); i != e; ++i) { in emitRegSave()
170 InstPrinter.printRegName(OS, RegList[i]); in emitRegSave()
398 void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
466 void emitRegSave(const SmallVectorImpl<unsigned> &RegList, bool isVector);
750 getStreamer().emitRegSave(RegList, isVector); in emitRegSave()
1446 void ARMELFStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
1452 for (size_t i = 0; i < RegList.size(); ++i) { in emitRegSave()
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| H A D | ARMTargetStreamer.cpp | 99 void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList, in emitRegSave() argument
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetCallingConv.td | 90 list<Register> RegList = regList;
97 list<Register> RegList = regList;
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| /freebsd-12.1/contrib/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 451 ArrayRef<MCPhysReg> RegList; in AnalyzeArguments() local
456 RegList = BuiltinRegList; in AnalyzeArguments()
459 RegList = CRegList; in AnalyzeArguments()
512 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
520 unsigned Reg = State.AllocateReg(RegList); in AnalyzeArguments()
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| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCStreamer.h | 138 virtual void emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 777 delete RegList.List; in ~MipsOperand()
820 struct RegListOp RegList; member
1365 int Size = RegList.List->size(); in isRegList16()
1369 unsigned R0 = RegList.List->front(); in isRegList16()
1370 unsigned R1 = RegList.List->back(); in isRegList16()
1375 int PrevReg = *RegList.List->begin(); in isRegList16()
1377 int Reg = (*(RegList.List))[i]; in isRegList16()
1441 return *(RegList.List); in getRegList()
1545 Op->RegList.List = new SmallVector<unsigned, 10>(Regs.begin(), Regs.end()); in CreateRegList()
1675 for (auto Reg : (*RegList.List)) in print()
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| /freebsd-12.1/contrib/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 58 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Split_64() local
62 if (unsigned Reg = State.AllocateReg(RegList)) { in CC_Sparc_Assign_Split_64()
73 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Split_64()
86 static const MCPhysReg RegList[] = { in CC_Sparc_Assign_Ret_Split_64() local
91 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
97 if (unsigned Reg = State.AllocateReg(RegList)) in CC_Sparc_Assign_Ret_Split_64()
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 980 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8; in analyzeStandardArguments() local
984 ArrayRef<MCPhysReg>(RegList, array_lengthof(RegList8))); in analyzeStandardArguments()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 2086 const SmallVectorImpl<unsigned> &RegList = getRegList(); in addRegListOperands() local
2088 I = RegList.begin(), E = RegList.end(); I != E; ++I) in addRegListOperands()
3331 const SmallVectorImpl<unsigned> &RegList = getRegList(); in print() local
3333 I = RegList.begin(), E = RegList.end(); I != E; ) { in print()
6889 auto &RegList = Op.getRegList(); in validateInstruction() local
6890 if (RegList.size() < 1 || RegList.size() > 16) in validateInstruction()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MicroMipsInstrInfo.td | 518 let Name = "RegList";
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 49 ArrayRef<MCPhysReg> RegList = makeArrayRef(RC->begin(), NumRegs); in allocateCCRegs() local
50 unsigned RegResult = State.AllocateReg(RegList); in allocateCCRegs()
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