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Searched refs:RegClassID (Results 1 – 8 of 8) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.h60 const char* getRegClassName(unsigned RegClassID) const;
63 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
H A DAMDGPUDisassembler.cpp374 const char* AMDGPUDisassembler::getRegClassName(unsigned RegClassID) const { in getRegClassName()
376 getRegClassName(&AMDGPUMCRegisterClasses[RegClassID]); in getRegClassName()
395 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand() argument
397 const auto& RegCl = AMDGPUMCRegisterClasses[RegClassID]; in createRegOperand()
399 return errOperand(Val, Twine(getRegClassName(RegClassID)) + in createRegOperand()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelDAGToDAG.cpp98 void SelectBuildVector(SDNode *N, unsigned RegClassID);
413 void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) { in SelectBuildVector() argument
418 SDValue RegClass = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
433 RegSeqArgs[0] = CurDAG->getTargetConstant(RegClassID, DL, MVT::i32); in SelectBuildVector()
528 unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts); in Select() local
529 SelectBuildVector(N, RegClassID); in Select()
2201 unsigned RegClassID; in Select() local
2207 case 2: RegClassID = R600::R600_Reg64RegClassID; break; in Select()
2210 RegClassID = R600::R600_Reg128VerticalRegClassID; in Select()
2212 RegClassID = R600::R600_Reg128RegClassID; in Select()
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/freebsd-12.1/contrib/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp815 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
1232 unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, in GetSIDIForRegClass() argument
1234 switch (RegClassID) { in GetSIDIForRegClass()
1268 int RegClassID = -1; in VerifyAndAdjustOperands() local
1289 if (RegClassID != -1 && in VerifyAndAdjustOperands()
1290 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1296 RegClassID = X86::GR64RegClassID; in VerifyAndAdjustOperands()
1298 RegClassID = X86::GR32RegClassID; in VerifyAndAdjustOperands()
1300 RegClassID = X86::GR16RegClassID; in VerifyAndAdjustOperands()
1307 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI); in VerifyAndAdjustOperands()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp519 unsigned RegClassID = ChainBegin->getDesc().OpInfo[0].RegClass; in scavengeRegister() local
520 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
H A DAArch64RegisterInfo.td623 let PredicateMethod = "isGPR64<AArch64::" # RC # "RegClassID>";
821 # Width # ", " # "AArch64::" # RegClass # "RegClassID>";
888 # RegClassSuffix # "RegClassID>";
927 let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
1104 let PredicateMethod = "isGPR64WithShiftExtend<AArch64::"#RegClass#"RegClassID, " # Scale # ">";
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1774 unsigned RegClassID, in DecodeGPRSeqPairsClassRegisterClass() argument
1782 unsigned Reg = AArch64MCRegisterClasses[RegClassID].getRegister(RegNo / 2); in DecodeGPRSeqPairsClassRegisterClass()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1159 template <unsigned RegClassID> bool isGPR64() const { in isGPR64()
1161 AArch64MCRegisterClasses[RegClassID].contains(getReg()); in isGPR64()
1164 template <unsigned RegClassID, int ExtWidth>
1169 if (isGPR64<RegClassID>() && getShiftExtendType() == AArch64_AM::LSL && in isGPR64WithShiftExtend()