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Searched refs:RegBytes (Results 1 – 4 of 4) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86SpeculativeLoadHardening.cpp2233 int RegBytes = TRI->getRegSizeInBits(*RC) / 8; in canHardenRegister() local
2234 if (RegBytes > 8) in canHardenRegister()
2248 if (RC == NOREXRegClasses[Log2_32(RegBytes)]) in canHardenRegister()
2254 return RC->hasSuperClassEq(GPRRegClasses[Log2_32(RegBytes)]); in canHardenRegister()
H A DX86InstrInfo.h84 unsigned getCMovFromCond(CondCode CC, unsigned RegBytes,
H A DX86InstrInfo.cpp2324 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes, in getCMovFromCond() argument
2363 switch(RegBytes) { in getCMovFromCond()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp4890 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedLoad() local
4891 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; in expandUnalignedLoad()
4903 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedLoad()
4904 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedLoad()
4918 Offset += RegBytes; in expandUnalignedLoad()
5046 unsigned RegBytes = RegVT.getSizeInBits() / 8; in expandUnalignedStore() local
5047 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; in expandUnalignedStore()
5060 SDValue PtrIncrement = DAG.getConstant(RegBytes, dl, PtrVT); in expandUnalignedStore()
5061 SDValue StackPtrIncrement = DAG.getConstant(RegBytes, dl, StackPtrVT); in expandUnalignedStore()
5077 Offset += RegBytes; in expandUnalignedStore()