Home
last modified time | relevance | path

Searched refs:ReadAdvance (Results 1 – 25 of 35) sorted by relevance

12

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td104 // These ReadAdvance entries are not used in the Falkor sched model.
105 def : ReadAdvance<ReadI, 0>;
106 def : ReadAdvance<ReadISReg, 0>;
107 def : ReadAdvance<ReadIEReg, 0>;
108 def : ReadAdvance<ReadIM, 0>;
109 def : ReadAdvance<ReadIMA, 0>;
110 def : ReadAdvance<ReadID, 0>;
111 def : ReadAdvance<ReadExtrHi, 0>;
112 def : ReadAdvance<ReadAdrBase, 0>;
113 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedKryo.td111 def : ReadAdvance<ReadI, 0>;
112 def : ReadAdvance<ReadISReg, 0>;
113 def : ReadAdvance<ReadIEReg, 0>;
114 def : ReadAdvance<ReadIM, 0>;
115 def : ReadAdvance<ReadIMA, 0>;
116 def : ReadAdvance<ReadID, 0>;
117 def : ReadAdvance<ReadExtrHi, 0>;
118 def : ReadAdvance<ReadAdrBase, 0>;
119 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedThunderX.td192 def : ReadAdvance<ReadExtrHi, 1>;
193 def : ReadAdvance<ReadAdrBase, 2>;
194 def : ReadAdvance<ReadVLD, 2>;
200 // ReadAdvance applies to Extended registers as well, even though there is
202 def : ReadAdvance<ReadI, 2, [WriteImm, WriteI,
226 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
230 def : ReadAdvance<ReadIMA, 2, [WriteImm, WriteI,
236 def : ReadAdvance<ReadID, 1, [WriteImm, WriteI,
H A DAArch64SchedA53.td149 def : ReadAdvance<ReadExtrHi, 0>;
150 def : ReadAdvance<ReadAdrBase, 0>;
151 def : ReadAdvance<ReadVLD, 0>;
156 // ReadAdvance applies to Extended registers as well, even though there is
158 def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
182 def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
186 def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
192 def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
H A DAArch64SchedExynosM1.td212 def : ReadAdvance<ReadI, 0>;
213 def : ReadAdvance<ReadISReg, 0>;
214 def : ReadAdvance<ReadIEReg, 0>;
215 def : ReadAdvance<ReadIM, 0>;
217 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
218 def : ReadAdvance<ReadID, 0>;
219 def : ReadAdvance<ReadExtrHi, 0>;
220 def : ReadAdvance<ReadAdrBase, 0>;
221 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedA57.td111 def : ReadAdvance<ReadI, 0>;
112 def : ReadAdvance<ReadISReg, 0>;
113 def : ReadAdvance<ReadIEReg, 0>;
114 def : ReadAdvance<ReadIM, 0>;
115 def : ReadAdvance<ReadIMA, 2, [WriteIM32, WriteIM64]>;
116 def : ReadAdvance<ReadID, 0>;
117 def : ReadAdvance<ReadExtrHi, 0>;
118 def : ReadAdvance<ReadAdrBase, 0>;
119 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedExynosM3.td259 def : ReadAdvance<ReadI, 0>;
260 def : ReadAdvance<ReadISReg, 0>;
261 def : ReadAdvance<ReadIEReg, 0>;
262 def : ReadAdvance<ReadIM, 0>;
264 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
265 def : ReadAdvance<ReadID, 0>;
266 def : ReadAdvance<ReadExtrHi, 0>;
267 def : ReadAdvance<ReadAdrBase, 0>;
268 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedCyclone.td185 def : ReadAdvance<ReadExtrHi, 1>;
634 def : ReadAdvance<ReadVLD, 5>;
864 def : ReadAdvance<ReadI, 0>;
865 def : ReadAdvance<ReadISReg, 0>;
866 def : ReadAdvance<ReadIEReg, 0>;
867 def : ReadAdvance<ReadIM, 0>;
868 def : ReadAdvance<ReadIMA, 0>;
869 def : ReadAdvance<ReadID, 0>;
H A DAArch64SchedExynosM4.td563 def : ReadAdvance<ReadI, 0>;
564 def : ReadAdvance<ReadISReg, 0>;
565 def : ReadAdvance<ReadIEReg, 0>;
566 def : ReadAdvance<ReadIM, 0>;
568 def : ReadAdvance<ReadIMA, 3, [WriteIM32, WriteIM64]>;
569 def : ReadAdvance<ReadID, 0>;
570 def : ReadAdvance<ReadExtrHi, 0>;
571 def : ReadAdvance<ReadAdrBase, 0>;
572 def : ReadAdvance<ReadVLD, 0>;
H A DAArch64SchedThunderX2T99.td356 def : ReadAdvance<ReadI, 0>;
357 def : ReadAdvance<ReadISReg, 0>;
358 def : ReadAdvance<ReadIEReg, 0>;
359 def : ReadAdvance<ReadIM, 0>;
360 def : ReadAdvance<ReadIMA, 0>;
361 def : ReadAdvance<ReadID, 0>;
362 def : ReadAdvance<ReadExtrHi, 0>;
363 def : ReadAdvance<ReadAdrBase, 0>;
364 def : ReadAdvance<ReadVLD, 0>;
/freebsd-12.1/contrib/llvm/lib/MCA/
H A DInstruction.cpp58 void WriteState::addUser(ReadState *User, int ReadAdvance) { in addUser() argument
63 unsigned ReadCycles = std::max(0, CyclesLeft - ReadAdvance); in addUser()
71 Users.emplace_back(User, ReadAdvance); in addUser()
/freebsd-12.1/contrib/llvm/lib/MCA/Stages/
H A DDispatchStage.cpp82 int ReadAdvance = STI.getReadAdvanceCycles(SC, RD.UseIndex, WriteResID); in updateRAWDependencies() local
83 WS.addUser(&RS, ReadAdvance); in updateRAWDependencies()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleR52.td88 def : ReadAdvance<ReadALU, 1>; // Operand needed in EX1 stage
90 def : ReadAdvance<ReadMUL, 0>;
91 def : ReadAdvance<ReadMAC, 0>;
128 def : ReadAdvance<ReadFPMUL, 1>; // mul operand read in F1
129 def : ReadAdvance<ReadFPMAC, 1>; // fp-mac operand read in F1
135 def : ReadAdvance<R52Read_ISS, 0>;
136 def : ReadAdvance<R52Read_EX1, 1>;
137 def : ReadAdvance<R52Read_EX2, 2>;
138 def : ReadAdvance<R52Read_F0, 0>;
139 def : ReadAdvance<R52Read_F1, 1>;
[all …]
H A DARMScheduleA57.td275 def : ReadAdvance<ReadMUL, 0>;
764 def : ReadAdvance<ReadFPMUL, 0>;
777 // def : ReadAdvance<A57ReadVFMA, 5, [A57WriteVFMA]>;
778 // def : ReadAdvance<A57ReadVFMA, 4, [A57WriteVMUL]>;
1039 // (4 or 3 ReadAdvance)
1052 // (4 or 3 ReadAdvance)
1065 // (4 or 3 ReadAdvance)
1078 // (3 or 2 ReadAdvance)
1103 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
1109 // 4cyc F1, 1cyc for accumulate sequence (3cyc ReadAdvance)
[all …]
H A DARMSchedule.td38 // ReadAdvance read resources allow us to define "pipeline by-passes" or
55 // def : ReadAdvance<ReadAdvanceALUsr, 3>;
H A DARMScheduleSwift.td137 def : ReadAdvance<ReadALU, 0>;
299 def : ReadAdvance<ReadMUL, 0>;
1073 def : ReadAdvance<ReadFPMUL, 0>;
1074 def : ReadAdvance<ReadFPMAC, 0>;
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86ScheduleSLM.td51 def : ReadAdvance<ReadAfterLd, 3>;
52 def : ReadAdvance<ReadAfterVecLd, 3>;
53 def : ReadAdvance<ReadAfterVecXLd, 3>;
54 def : ReadAdvance<ReadAfterVecYLd, 3>;
H A DX86ScheduleAtom.td45 def : ReadAdvance<ReadAfterLd, 3>;
46 def : ReadAdvance<ReadAfterVecLd, 3>;
47 def : ReadAdvance<ReadAfterVecXLd, 3>;
48 def : ReadAdvance<ReadAfterVecYLd, 3>;
H A DX86ScheduleBtVer2.td104 def : ReadAdvance<ReadAfterLd, 3>;
108 def : ReadAdvance<ReadAfterVecLd, 5>;
109 def : ReadAdvance<ReadAfterVecXLd, 5>;
110 def : ReadAdvance<ReadAfterVecYLd, 5>;
H A DX86ScheduleBdVer2.td246 def : ReadAdvance<ReadAfterLd, 4>;
250 def : ReadAdvance<ReadAfterVecLd, 5>;
251 def : ReadAdvance<ReadAfterVecXLd, 5>;
252 def : ReadAdvance<ReadAfterVecYLd, 5>;
H A DX86SchedSandyBridge.td72 def : ReadAdvance<ReadAfterLd, 5>;
76 def : ReadAdvance<ReadAfterVecLd, 5>;
77 def : ReadAdvance<ReadAfterVecXLd, 6>;
78 def : ReadAdvance<ReadAfterVecYLd, 7>;
H A DX86ScheduleZnver1.td91 def : ReadAdvance<ReadAfterLd, 4>;
94 def : ReadAdvance<ReadAfterVecLd, 8>;
95 def : ReadAdvance<ReadAfterVecXLd, 8>;
96 def : ReadAdvance<ReadAfterVecYLd, 8>;
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DSubtargetEmitter.cpp1129 Record *ReadAdvance = in GenSchedClassTables() local
1131 if (!ReadAdvance) in GenSchedClassTables()
1135 if (ReadAdvance->getValueAsBit("Unsupported")) { in GenSchedClassTables()
1139 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites"); in GenSchedClassTables()
1153 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles"); in GenSchedClassTables()
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSchedule.td27 // each subtarget, define WriteRes and ReadAdvance to associate
313 // Define values common to ReadAdvance and SchedReadAdvance.
325 // A processor may define a ReadAdvance associated with a SchedRead
330 // A ReadAdvance may be associated with a list of SchedWrites
335 class ReadAdvance<SchedRead read, int cycles, list<SchedWrite> writes = []>
/freebsd-12.1/contrib/llvm/include/llvm/MCA/
H A DInstruction.h155 void addUser(ReadState *Use, int ReadAdvance);

12