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Searched refs:ROR (Results 1 – 25 of 31) sorted by relevance

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/freebsd-12.1/crypto/openssl/crypto/sha/asm/
H A Dsha512-ppc.pl84 $ROR="rotrdi";
96 $ROR="rotrwi";
134 $ROR $a0,$e,$Sigma1[0]
135 $ROR $a1,$e,$Sigma1[1]
140 $ROR $a1,$a1,`$Sigma1[2]-$Sigma1[1]`
147 $ROR $a0,$a,$Sigma0[0]
148 $ROR $a1,$a,$Sigma0[1]
173 $ROR $a0,@X[($i+1)%16],$sigma0[0]
174 $ROR $a1,@X[($i+1)%16],$sigma0[1]
175 $ROR $t0,@X[($i+14)%16],$sigma1[0]
[all …]
/freebsd-12.1/secure/lib/libcrypto/arm/
H A Dsha1-armv4-large.S51 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
57 add r7,r7,r3,ror#27 @ E+=ROR(A,27)
76 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
82 add r6,r6,r7,ror#27 @ E+=ROR(A,27)
101 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
107 add r5,r5,r6,ror#27 @ E+=ROR(A,27)
126 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
132 add r4,r4,r5,ror#27 @ E+=ROR(A,27)
151 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
157 add r3,r3,r4,ror#27 @ E+=ROR(A,27)
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64AddressingModes.h38 ROR, enumerator
59 case AArch64_AM::ROR: return "ror"; in getShiftExtendName()
80 case 3: return AArch64_AM::ROR; in getShiftType()
108 case AArch64_AM::ROR: STEnc = 3; break; in getShifterImm()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedPredExynos.td132 // Identify EXTR as the alias for ROR (immediate).
H A DAArch64SchedPredicates.td52 def CheckShiftROR : CheckImmOperand_s<3, "AArch64_AM::ROR">;
H A DAArch64ISelDAGToDAG.cpp336 return AArch64_AM::ROR; in getShiftTypeForNode()
398 if (!AllowROR && ShType == AArch64_AM::ROR) in SelectShiftedRegister()
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.h42 ROR, ///< Bit rotate right. enumerator
H A DAVRISelLowering.cpp259 NODE(ROR); in getTargetNodeName()
321 Opc8 = AVRISD::ROR; in LowerShifts()
/freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/
H A DARMUtils.h182 static inline uint32_t ROR(const uint32_t value, const uint32_t amount, in ROR() function
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Utils/
H A DAArch64BaseInfo.h406 ROR, enumerator
/freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/
H A DEmulateInstructionARM.cpp1765 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRtPCRelative()
6370 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRImmediateARM()
6509 R[t] = ROR(data, 8*UInt(address<1:0>)); in EmulateLDRRegister()
8359 rotated = ROR(R[m], rotation); in EmulateSXTB()
8414 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTB()
8444 rotated = ROR(R[m], rotation); in EmulateSXTH()
8499 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateSXTH()
8529 rotated = ROR(R[m], rotation); in EmulateUXTB()
8584 uint64_t rotated = ROR(Rm, rotation, &success); in EmulateUXTB()
8612 rotated = ROR(R[m], rotation); in EmulateUXTH()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86SchedSandyBridge.td971 "ROR(8|16|32|64)m(1|i)")>;
1016 "ROR(8|16|32|64)mCL",
H A DX86SchedBroadwell.td1104 "ROR(8|16|32|64)m(1|i)")>;
1173 "ROR(8|16|32|64)mCL",
H A DX86SchedHaswell.td1183 "ROR(8|16|32|64)m(1|i)")>;
1305 "ROR(8|16|32|64)mCL",
H A DX86SchedSkylakeClient.td1184 "ROR(8|16|32|64)m(1|i)")>;
1259 "ROR(8|16|32|64)mCL",
H A DX86ScheduleAtom.td502 def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m",
H A DX86SchedSkylakeServer.td1447 "ROR(8|16|32|64)m(1|i)")>;
1611 "ROR(8|16|32|64)mCL",
H A DX86InstrCompiler.td1758 // ROL/ROR instructions allow a stronger mask optimization than shift for 8- and
1788 defm : MaskedRotateAmountPats<rotr, "ROR">;
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp1223 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR || in isShifter()
1326 ST == AArch64_AM::ASR || ST == AArch64_AM::ROR) && in isLogicalShifter()
2753 .Case("ror", AArch64_AM::ROR) in tryParseOptionalShiftExtend()
2775 ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR || in tryParseOptionalShiftExtend()
/freebsd-12.1/sys/dev/axgbe/
H A Dxgbe-dev.c1906 XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1); in xgbe_config_mmc()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCInstrInfo.td236 defm ROR : ArcBinaryEXT5Inst<0b000011, "ror">;
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleSwift.td155 // ASR,LSL,ROR,RRX
H A DARMScheduleA57.td228 // (ASR, LSL, LSR, ROR, RRX)=MOVsi, MVN
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2523 case Mips::ROR: in tryExpandInstruction()
4425 if (Inst.getOpcode() == Mips::ROR) { in expandRotation()
4441 case Mips::ROR: in expandRotation()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsInstrInfo.td2543 def ROR : MipsAsmPseudoInst<(outs),
2550 (ROR GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;

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