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Searched refs:RO (Results 1 – 25 of 54) sorted by relevance

123

/freebsd-12.1/contrib/ntp/libparse/
H A Dinfo_trimble.c57 { CMD_RALMANAC, "CMD_RALMANAC", "almanac data for sat (0x40)", "gps_almanac", RO },
58 { CMD_RCURTIME, "CMD_RCURTIME", "GPS time (0x41)", "gps_time", RO },
61 { CMD_RBEST4, "CMD_RBEST4", "best 4 satellite selection (0x44)", "trimble_best4", RO|DEF },
62 { CMD_RVERSION, "CMD_RVERSION", "software version (0x45)", "trimble_version", RO|DEF },
65 { CMD_RMESSAGE, "CMD_RMESSAGE", "GPS system message (0x48)", "gps-message", RO|DEF },
70 { CMD_ROSCOFFSET, "CMD_ROSCOFFSET", "oscillator offset (0x4D)", "trimble_oscoffset", RO },
72 { CMD_RUTCPARAM, "CMD_RUTCPARAM", "UTC parameters (0x4F)", "gps_utc_correction", RO|DEF },
75 { CMD_RIOOPTIONS, "CMD_RIOOPTIONS", "I/O options (0x55)", "trimble_iooptions", RO },
79 { CMD_RLASTRAW, "CMD_RLASTRAW", "last raw measurement (0x5A)", "trimble_lastraw", RO },
82 { CMD_RADDITFIX, "CMD_RADDITFIX", "additional fix data (0x5E)", "trimble_addfix", RO },
[all …]
/freebsd-12.1/contrib/ntp/ntpd/
H A Dntp_control.c348 { CS_POLL, RO, "tc" }, /* 8 */
360 { CS_TAI, RO, "tai" }, /* 20 */
505 { CP_LEAP, RO, "leap" }, /* 8 */
515 { CP_ORG, RO, "org" }, /* 18 */
516 { CP_REC, RO, "rec" }, /* 19 */
530 { CP_SENT, RO, "sent" }, /* 33 */
533 { CP_TTL, RO, "ttl" }, /* 36 */
535 { CP_IN, RO, "in" }, /* 38 */
536 { CP_OUT, RO, "out" }, /* 39 */
618 { CC_TYPE, RO, "type" }, /* 1 */
[all …]
H A Drefclock_neoclock4x.c738 tt = add_var(&out->kv_list, sizeof(tmpbuf)-1, RO|DEF); in neoclock4x_control()
741 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
743 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
745 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
747 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
754 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
761 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
768 tt = add_var(&out->kv_list, 80, RO|DEF); in neoclock4x_control()
770 tt = add_var(&out->kv_list, 40, RO|DEF); in neoclock4x_control()
772 tt = add_var(&out->kv_list, 80, RO|DEF); in neoclock4x_control()
[all …]
H A Drefclock_parse.c3559 tt = add_var(&out->kv_list, 80, RO); in parse_control()
3566 tt = add_var(&out->kv_list, 80, RO|DEF); in parse_control()
3570 start = tt = add_var(&out->kv_list, 128, RO|DEF); in parse_control()
3590 start = tt = add_var(&out->kv_list, 512, RO|DEF); in parse_control()
3624 start = tt = add_var(&out->kv_list, 80, RO|DEF); in parse_control()
3685 tt = add_var(&out->kv_list, 32, RO); in parse_control()
3688 tt = add_var(&out->kv_list, 80, RO); in parse_control()
3691 tt = add_var(&out->kv_list, 128, RO); in parse_control()
4415 set_var(&parse->kv, buffer, sizeof(buffer), RO|DEF); in gps16x_message()
4431 set_var(&parse->kv, buffer, sizeof(buffer), RO|DEF); in gps16x_message()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td212 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
214 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
276 InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr),
284 InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr),
305 MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt),
307 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
319 MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
321 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
327 MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
329 [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>;
[all …]
H A DMipsInstrInfo.td1363 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1365 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
1376 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
1395 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
1397 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
1414 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
1463 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
1518 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1530 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
1842 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, SizeOpnd:$size, RO:$src),
[all …]
H A DMicroMipsDSPInstrInfo.td218 RegisterOperand RO, Operand ImmOpnd> {
219 dag OutOperandList = (outs RO:$rt);
220 dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
222 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
254 InstrItinClass itin, RegisterOperand RO> {
255 dag OutOperandList = (outs RO:$rd);
256 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs);
258 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
337 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
340 dag InOperandList = (ins RO:$ac);
[all …]
H A DMips64InstrInfo.td437 class Count1s<string opstr, RegisterOperand RO>:
438 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
439 [(set RO:$rd, (ctpop RO:$rs))], II_POP, FrmR, opstr> {
443 class ExtsCins<string opstr, InstrItinClass itin, RegisterOperand RO,
445 InstSE<(outs RO:$rt), (ins RO:$rs, uimm5:$pos, uimm5:$lenm1),
447 [(set RO:$rt, (Op RO:$rs, PosImm:$pos, imm:$lenm1))],
472 InstSE<(outs), (ins RO:$rs, ImmOp:$p, opnd:$offset),
482 class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> :
483 InstSE<(outs RO:$rt, uimm16:$imm16), (ins),
1030 class LoadImmediate64<string instr_asm, Operand Od, RegisterOperand RO> :
[all …]
H A DMipsDSPInstrInfo.td329 RegisterOperand RO> {
330 dag OutOperandList = (outs RO:$rd);
333 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
340 dag OutOperandList = (outs RO:$rd);
341 dag InOperandList = (ins RO:$rt, GPR32Opnd:$rs_sa);
343 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs_sa))];
351 dag OutOperandList = (outs RO:$rd);
352 dag InOperandList = (ins RO:$rt, ImmOpnd:$rs_sa);
354 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, ImmPat:$rs_sa))];
500 dag InOperandList = (ins RO:$ac);
[all …]
H A DMips32r6InstrInfo.td1109 class TailCallRegR6<Instruction JumpInst, Register RT, RegisterOperand RO> :
1110 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
1111 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)>;
1115 RegisterOperand RO> :
1116 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1118 PseudoInstExpansion<(JumpInst RT:$rt, RO:$rs)> {
H A DMicroMips32r6InstrInfo.td456 class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
457 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
458 [(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
491 class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
492 : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
641 class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
643 dag InOperandList = (ins RO:$rs);
644 dag OutOperandList = (outs RO:$rt);
1077 class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO,
1079 : Store<opstr, RO>, MMR6Arch<opstr> {
[all …]
H A DMipsInstrFPU.td737 class BuildPairF64Base<RegisterOperand RO> :
738 PseudoSE<(outs RO:$dst), (ins GPR32Opnd:$lo, GPR32Opnd:$hi),
739 [(set RO:$dst, (MipsBuildPairF64 GPR32Opnd:$lo, GPR32Opnd:$hi))],
751 class ExtractElementF64Base<RegisterOperand RO> :
752 PseudoSE<(outs GPR32Opnd:$dst), (ins RO:$src, i32imm:$n),
753 [(set GPR32Opnd:$dst, (MipsExtractElementF64 RO:$src, imm:$n))],
/freebsd-12.1/sys/dev/aic7xxx/
H A Daic79xx.reg216 access_mode RO
290 access_mode RO
433 access_mode RO
458 access_mode RO
639 access_mode RO
650 access_mode RO
661 access_mode RO
687 access_mode RO
697 access_mode RO
707 access_mode RO
[all …]
H A Daic7xxx.reg108 access_mode RO
281 access_mode RO
314 access_mode RO
330 access_mode RO
346 access_mode RO
423 access_mode RO
633 access_mode RO
639 access_mode RO
651 access_mode RO
658 access_mode RO
[all …]
/freebsd-12.1/sys/dts/powerpc/
H A Dp1020rdb.dts100 label = "NOR (RO) Vitesse-7385 Firmware";
107 label = "NOR (RO) DTB Image";
114 label = "NOR (RO) Linux Kernel Image";
129 label = "NOR (RO) U-Boot Image";
145 label = "NAND (RO) U-Boot Image";
152 label = "NAND (RO) DTB Image";
159 label = "NAND (RO) Linux Kernel Image";
166 label = "NAND (RO) Compressed RFS Image";
289 label = "SPI (RO) U-Boot Image";
296 label = "SPI (RO) DTB Image";
[all …]
/freebsd-12.1/usr.sbin/cron/doc/
H A DMAIL12 Status: RO
30 Status: RO
56 Status: RO
85 Status: RO
97 Status: RO
111 Status: RO
130 Status: RO
159 Status: RO
207 Status: RO
231 Status: RO
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp820 const MachineOperand &RO = PN->getOperand(i), &BO = PN->getOperand(i+1); in updatePhiNodes() local
822 SR = RO.getReg(), SSR = RO.getSubReg(); in updatePhiNodes()
824 TR = RO.getReg(), TSR = RO.getSubReg(); in updatePhiNodes()
826 FR = RO.getReg(), FSR = RO.getSubReg(); in updatePhiNodes()
H A DHexagonGenInsert.cpp383 OrderedRegisterList(const RegisterOrdering &RO) in OrderedRegisterList() argument
384 : MaxSize(MaxORLSize), Ord(RO) {} in OrderedRegisterList()
525 void buildOrderingMF(RegisterOrdering &RO) const;
526 void buildOrderingBT(RegisterOrdering &RB, RegisterOrdering &RO) const;
593 void HexagonGenInsert::buildOrderingMF(RegisterOrdering &RO) const { in buildOrderingMF()
613 RO.insert(std::make_pair(R, Index++)); in buildOrderingMF()
624 RegisterOrdering &RO) const { in buildOrderingBT()
638 RO.insert(std::make_pair(VRs[i], i)); in buildOrderingBT()
/freebsd-12.1/contrib/llvm/lib/Target/X86/MCTargetDesc/
H A DX86WinCOFFTargetStreamer.cpp352 for (RegSaveOffset RO : RegSaveOffsets) in emitFrameDataRecord() local
353 FuncOS << printFPOReg(MRI, RO.Reg) << ' ' << CFAVar << ' ' << RO.Offset in emitFrameDataRecord()
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DAsmWriterEmitter.cpp856 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; in EmitPrintAliasInstruction() local
858 switch (RO.Kind) { in EmitPrintAliasInstruction()
860 const Record *Rec = RO.getRecord(); in EmitPrintAliasInstruction()
861 StringRef ROName = RO.getName(); in EmitPrintAliasInstruction()
941 MIOpNum += RO.getMINumOperands(); in EmitPrintAliasInstruction()
/freebsd-12.1/sys/dev/aic7xxx/aicasm/
H A Daicasm_symbol.h67 RO = 0x01, enumerator
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCodeGenFunction.cpp2423 CodeGenFunction::FormResolverCondition(const MultiVersionResolverOption &RO) { in FormResolverCondition() argument
2426 if (!RO.Conditions.Architecture.empty()) in FormResolverCondition()
2427 Condition = EmitX86CpuIs(RO.Conditions.Architecture); in FormResolverCondition()
2429 if (!RO.Conditions.Features.empty()) { in FormResolverCondition()
2430 llvm::Value *FeatureCond = EmitX86CpuSupports(RO.Conditions.Features); in FormResolverCondition()
2475 for (const MultiVersionResolverOption &RO : Options) { in EmitMultiVersionResolver() local
2477 llvm::Value *Condition = FormResolverCondition(RO); in EmitMultiVersionResolver()
2481 assert(&RO == Options.end() - 1 && in EmitMultiVersionResolver()
2483 CreateMultiVersionResolverReturn(CGM, Resolver, Builder, RO.Function, in EmitMultiVersionResolver()
2490 CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder, RO.Function, in EmitMultiVersionResolver()
/freebsd-12.1/contrib/llvm/tools/llvm-diff/
H A DDifferenceEngine.cpp372 Value *LO = L->getOperand(I), *RO = R->getOperand(I); in diff() local
373 if (!equivalentAsOperands(LO, RO)) { in diff()
374 if (Complain) Engine.logf("operands %l and %r differ") << LO << RO; in diff()
/freebsd-12.1/contrib/llvm/tools/clang/include/clang/Basic/
H A DOpenCLImageTypes.def32 IMAGE_TYPE(Type, Id##RO, Id##ROTy, read_only, ro)
/freebsd-12.1/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/
H A DRegionStore.cpp116 const RegionOffset &RO = R->getAsOffset(); in Make() local
117 if (RO.hasSymbolicOffset()) in Make()
118 return BindingKey(cast<SubRegion>(R), cast<SubRegion>(RO.getRegion()), k); in Make()
120 return BindingKey(RO.getRegion(), RO.getOffset(), k); in Make()
1149 const RegionOffset &RO = baseR->getAsOffset(); in VisitCluster() local
1151 if (RO.hasSymbolicOffset()) { in VisitCluster()
1159 uint64_t LowerOffset = RO.getOffset(); in VisitCluster()

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