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Searched refs:RADEON_CLOCK_CNTL_INDEX (Results 1 – 8 of 8) sorted by relevance

/freebsd-12.1/sys/powerpc/powermac/
H A Datibl.c70 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
174 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, (reg & 0x3f)); in atibl_pll_rreg()
181 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_rreg()
183 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp); in atibl_pll_rreg()
185 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save); in atibl_pll_rreg()
195 bus_write_1(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, in atibl_pll_wreg()
204 save = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX); in atibl_pll_wreg()
206 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, tmp); in atibl_pll_wreg()
208 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_INDEX, save); in atibl_pll_wreg()
/freebsd-12.1/sys/dev/drm2/radeon/
H A Dradeon_legacy_crtc.c913 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
934 WREG32_P(RADEON_CLOCK_CNTL_INDEX, in radeon_set_pll()
H A Dradeon_drv.h527 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
1865 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, \
H A Dr100.c2984 save = RREG32(RADEON_CLOCK_CNTL_INDEX); in r100_pll_errata_after_data()
2986 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp); in r100_pll_errata_after_data()
2988 WREG32(RADEON_CLOCK_CNTL_INDEX, save); in r100_pll_errata_after_data()
2996 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f); in r100_pll_rreg()
3005 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN)); in r100_pll_wreg()
H A Dradeon_legacy_tv.c289 WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); in radeon_wait_pll_lock()
H A Dradeon_legacy_encoders.c239 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); in radeon_legacy_lvds_mode_set()
H A Dradeon_reg.h349 #define RADEON_CLOCK_CNTL_INDEX 0x0008 macro
H A Dradeon_combios.c1229 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; in radeon_legacy_get_lvds_info_from_regs()