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Searched refs:RADEON_CLOCK_CNTL_DATA (Results 1 – 5 of 5) sorted by relevance

/freebsd-12.1/sys/powerpc/powermac/
H A Datibl.c69 #define RADEON_CLOCK_CNTL_DATA 0x000c macro
175 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
178 data = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
184 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_rreg()
197 (void)bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
200 bus_write_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA, val); in atibl_pll_wreg()
207 tmp = bus_read_4(sc->sc_memr, RADEON_CLOCK_CNTL_DATA); in atibl_pll_wreg()
/freebsd-12.1/sys/dev/drm2/radeon/
H A Dradeon_legacy_tv.c291 WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); in radeon_wait_pll_lock()
293 if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) in radeon_wait_pll_lock()
H A Dradeon_drv.h525 #define RADEON_CLOCK_CNTL_DATA 0x000c macro
1867 RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, (val)); \
H A Dr100.c2962 (void)RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_index()
2987 tmp = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_errata_after_data()
2998 data = RREG32(RADEON_CLOCK_CNTL_DATA); in r100_pll_rreg()
3007 WREG32(RADEON_CLOCK_CNTL_DATA, v); in r100_pll_wreg()
H A Dradeon_reg.h348 #define RADEON_CLOCK_CNTL_DATA 0x000c macro