Searched refs:QPR (Results 1 – 4 of 4) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 2817 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), 2900 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2945 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 2964 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin, 5396 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, 5400 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>, 5417 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>, 5421 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>, 5433 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), 5447 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), [all …]
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| H A D | ARMRegisterInfo.td | 359 def QPR : RegisterClass<"ARM", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, v8f16], 128, 362 let AltOrders = [(rotl QPR, 8)]; 367 // Subset of QPR that have 32-bit SPR subregs. 369 128, (trunc QPR, 8)> { 373 // Subset of QPR that have DPR_8 and SPR_8 subregs. 375 128, (trunc QPR, 4)> { 390 128, (interleave QPR, TuplesOE2D)> { 393 let AltOrders = [(add (rotl QPR, 8), (rotl DPair, 16))]; 422 def Tuples2Q : RegisterTuples<[qsub_0, qsub_1], [(shl QPR, 0), (shl QPR, 1)]>;
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| H A D | ARMRegisterBanks.td | 14 def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;
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| H A D | A15SDOptimizer.cpp | 70 bool QPR = false); 421 unsigned Lane, bool QPR) { in createDupLane() argument 422 unsigned Out = MRI->createVirtualRegister(QPR ? &ARM::QPRRegClass : in createDupLane() 425 TII->get(QPR ? ARM::VDUPLN32q : ARM::VDUPLN32d), Out) in createDupLane()
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