Searched refs:PrefReg (Results 1 – 4 of 4) sorted by relevance
758 void setRegAllocationHint(unsigned VReg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument762 RegAllocHints[VReg].second.push_back(PrefReg); in setRegAllocationHint()767 void addRegAllocationHint(unsigned VReg, unsigned PrefReg) { in addRegAllocationHint() argument769 RegAllocHints[VReg].second.push_back(PrefReg); in addRegAllocationHint()774 void setSimpleHint(unsigned VReg, unsigned PrefReg) { in setSimpleHint() argument775 setRegAllocationHint(VReg, /*Type=*/0, PrefReg); in setSimpleHint()
83 PrefReg, ///< Block entry/exit prefers a register. enumerator
142 case PrefReg: in addBias()
1185 BC.Entry = BI.LiveIn ? SpillPlacement::PrefReg : SpillPlacement::DontCare; in addSplitConstraints()1188 ? SpillPlacement::PrefReg in addSplitConstraints()1609 Ins += RegIn != (BC.Entry == SpillPlacement::PrefReg); in calcGlobalSplitCost()1611 Ins += RegOut != (BC.Exit == SpillPlacement::PrefReg); in calcGlobalSplitCost()