| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonEarlyIfConv.cpp | 132 unsigned PredR = 0; member
201 unsigned PredR, bool IfTrue);
254 unsigned PredR = T1I->getOperand(0).getReg(); in matchFlowPattern() local
334 FP = FlowPattern(B, PredR, TB, FB, JB); in matchFlowPattern()
711 unsigned PredR, bool IfTrue) { in predicateInstr() argument
729 MIB.addReg(PredR); in predicateInstr()
745 .addReg(PredR) in predicateInstr()
762 unsigned PredR, bool IfTrue) { in predicateBlockNB() argument
804 .addReg(PredR) in buildMux()
916 .addReg(FP.PredR) in convert()
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| H A D | HexagonGenMux.cpp | 93 unsigned PredR = 0; member
109 unsigned DefR, PredR; member
116 : At(It), DefR(DR), PredR(PR), SrcT(TOp), SrcF(FOp), Def1(&D1), in MuxInfo()
257 if (F != CM.end() && F->second.PredR != PR) { in genMuxInBlock()
264 F->second.PredR = PR; in genMuxInBlock()
339 .addReg(MX.PredR) in genMuxInBlock()
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| H A D | HexagonExpandCondsets.cpp | 221 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond);
228 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
746 MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { in getReachingDefForPred() argument
769 if (RR.Reg == PredR) { in getReachingDefForPred()
909 unsigned PredR, bool Cond, MachineBasicBlock::iterator First, in renameInRange() argument
918 if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) in renameInRange()
958 unsigned PredR = MP.getReg(); in predicate() local
959 MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); in predicate()
976 if (!I->modifiesRegister(PredR, nullptr)) in predicate()
989 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) in predicate()
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| H A D | HexagonHardwareLoops.cpp | 462 unsigned PredR, PredPos, PredRegFlags; in findInductionRegister() local
463 if (!TII->getPredReg(Cond, PredR, PredPos, PredRegFlags)) in findInductionRegister()
466 MachineInstr *PredI = MRI->getVRegDef(PredR); in findInductionRegister()
1337 unsigned PredR = CmpI->getOperand(0).getReg(); in orderBumpCompare() local
1345 if (MO.getReg() == PredR) // Found an intervening use of PredR. in orderBumpCompare()
1915 unsigned PredR = PN->getOperand(i).getReg(); in createPreheaderForLoop() local
1921 MachineOperand MO = MachineOperand::CreateReg(PredR, false); in createPreheaderForLoop()
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| H A D | HexagonISelLowering.cpp | 290 unsigned PredR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in LowerCallResult() local
291 SDValue TPR = DAG.getCopyToReg(FR0.getValue(1), dl, PredR, in LowerCallResult()
297 RetVal = DAG.getCopyFromReg(TPR.getValue(0), dl, PredR, MVT::i1); in LowerCallResult()
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| /freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAndOrXor.cpp | 478 if (PredR != NewCC) in foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed()
1128 PredR == ICmpInst::ICMP_UGE || PredR == ICmpInst::ICMP_ULE || in foldAndOfICmps()
1130 PredR == ICmpInst::ICMP_SGE || PredR == ICmpInst::ICMP_SLE) in foldAndOfICmps()
1163 switch (PredR) { in foldAndOfICmps()
1183 switch (PredR) { in foldAndOfICmps()
1196 switch (PredR) { in foldAndOfICmps()
1220 PredR = FCmpInst::getSwappedPredicate(PredR); in foldLogicOfFCmps()
2114 PredR == ICmpInst::ICMP_UGE || PredR == ICmpInst::ICMP_ULE || in foldOrOfICmps()
2116 PredR == ICmpInst::ICMP_SGE || PredR == ICmpInst::ICMP_SLE) in foldOrOfICmps()
2149 switch (PredR) { in foldOrOfICmps()
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| /freebsd-12.1/contrib/llvm/lib/Analysis/ |
| H A D | InstructionSimplify.cpp | 1712 FCmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate(); in simplifyAndOrOfFCmps() local
1713 if ((PredL == FCmpInst::FCMP_ORD && PredR == FCmpInst::FCMP_ORD && IsAnd) || in simplifyAndOrOfFCmps()
1714 (PredL == FCmpInst::FCMP_UNO && PredR == FCmpInst::FCMP_UNO && !IsAnd)) { in simplifyAndOrOfFCmps()
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