Searched refs:PredOp (Results 1 – 3 of 3) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 215 unsigned DstSR, const MachineOperand &PredOp, bool PredSense,
226 const MachineOperand &PredOp, bool Cond,
625 unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, in genCondTfrFor() argument
639 unsigned PredState = getRegState(PredOp) & ~RegState::Kill; in genCondTfrFor()
648 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
653 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg()) in genCondTfrFor()
857 const MachineOperand &PredOp, bool Cond, in predicateAt() argument
886 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, in predicateAt()
887 PredOp.getSubReg()); in predicateAt()
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| H A D | HexagonGenMux.cpp | 246 MachineOperand &PredOp = MI->getOperand(1); in genMuxInBlock() local
247 if (PredOp.isUndef()) in genMuxInBlock()
250 unsigned PR = PredOp.getReg(); in genMuxInBlock()
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| H A D | HexagonISelLowering.cpp | 871 SDValue PredOp = Op.getOperand(0); in LowerVSELECT() local
879 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2); in LowerVSELECT()
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