1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 1997,1998 Maxim Bolotin and Oleg Sharoiko.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 */
30
31 /*
32 * $FreeBSD$
33 */
34
35 #include <sys/rman.h>
36
37 #define CS_89x0_IO_PORTS 0x0020
38
39 #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
40 /* offset 2h -> Model/Product Number */
41 /* offset 3h -> Chip Revision Number */
42
43 #define PP_ISAIOB 0x0020 /* IO base address */
44 #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
45 #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
46 #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
47 #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
48 #define PP_ISASOF 0x0026 /* ISA DMA offset */
49 #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
50 #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
51 #define PP_CS8920_ISAMemB 0x0348 /* Memory base */
52
53 /* EEPROM data and command registers */
54 #define PP_EECMD 0x0040 /* NVR Interface Command register */
55 #define PP_EEData 0x0042 /* NVR Interface Data Register */
56 #define PP_DebugReg 0x0044 /* Debug Register */
57
58 #define PP_RxCFG 0x0102 /* Rx Bus config */
59 #define PP_RxCTL 0x0104 /* Receive Control Register */
60 #define PP_TxCFG 0x0106 /* Transmit Config Register */
61 #define PP_TxCMD 0x0108 /* Transmit Command Register */
62 #define PP_BufCFG 0x010A /* Bus configuration Register */
63 #define PP_LineCTL 0x0112 /* Line Config Register */
64 #define PP_SelfCTL 0x0114 /* Self Command Register */
65 #define PP_BusCTL 0x0116 /* ISA bus control Register */
66 #define PP_TestCTL 0x0118 /* Test Register */
67 #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
68
69 #define PP_ISQ 0x0120 /* Interrupt Status */
70 #define PP_RxEvent 0x0124 /* Rx Event Register */
71 #define PP_TxEvent 0x0128 /* Tx Event Register */
72 #define PP_BufEvent 0x012C /* Bus Event Register */
73 #define PP_RxMiss 0x0130 /* Receive Miss Count */
74 #define PP_TxCol 0x0132 /* Transmit Collision Count */
75 #define PP_LineST 0x0134 /* Line State Register */
76 #define PP_SelfST 0x0136 /* Self State register */
77 #define PP_BusST 0x0138 /* Bus Status */
78 #define PP_TDR 0x013C /* Time Domain Reflectometry */
79 #define PP_AutoNegST 0x013E /* Auto Neg Status */
80 #define PP_TxCommand 0x0144 /* Tx Command */
81 #define PP_TxLength 0x0146 /* Tx Length */
82 #define PP_LAF 0x0150 /* Hash Table */
83 #define PP_IA 0x0158 /* Physical Address Register */
84
85 #define PP_RxStatus 0x0400 /* Receive start of frame */
86 #define PP_RxLength 0x0402 /* Receive Length of frame */
87 #define PP_RxFrame 0x0404 /* Receive frame pointer */
88 #define PP_TxFrame 0x0A00 /* Transmit frame pointer */
89
90 /*
91 * Primary I/O Base Address. If no I/O base is supplied by the user, then this
92 * can be used as the default I/O base to access the PacketPage Area.
93 */
94 #define DEFAULTIOBASE 0x0300
95 #define FIRST_IO 0x020C /* First I/O port to check */
96 #define LAST_IO 0x037C /* Last I/O port to check (+10h) */
97 #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
98 #define ADD_SIG 0x3000 /* Expected ID signature */
99
100 #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
101
102 #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
103
104 /* Mask to find out the types of registers */
105 #define REG_TYPE_MASK 0x001F
106
107 /* Eeprom Commands */
108 #define ERSE_WR_ENBL 0x00F0
109 #define ERSE_WR_DISABLE 0x0000
110
111 /* Defines Control/Config register quintuplet numbers */
112 #define RX_BUF_CFG 0x0003
113 #define RX_CONTROL 0x0005
114 #define TX_CFG 0x0007
115 #define TX_COMMAND 0x0009
116 #define BUF_CFG 0x000B
117 #define LINE_CONTROL 0x0013
118 #define SELF_CONTROL 0x0015
119 #define BUS_CONTROL 0x0017
120 #define TEST_CONTROL 0x0019
121
122 /* Defines Status/Count registers quintuplet numbers */
123 #define RX_EVENT 0x0004
124 #define TX_EVENT 0x0008
125 #define BUF_EVENT 0x000C
126 #define RX_MISS_COUNT 0x0010
127 #define TX_COL_COUNT 0x0012
128 #define LINE_STATUS 0x0014
129 #define SELF_STATUS 0x0016
130 #define BUS_STATUS 0x0018
131 #define TDR 0x001C
132
133 /*
134 * PP_RxCFG - Receive Configuration and Interrupt Mask
135 * bit definition - Read/write
136 */
137 #define SKIP_1 0x0040
138 #define RX_STREAM_ENBL 0x0080
139 #define RX_OK_ENBL 0x0100
140 #define RX_DMA_ONLY 0x0200
141 #define AUTO_RX_DMA 0x0400
142 #define BUFFER_CRC 0x0800
143 #define RX_CRC_ERROR_ENBL 0x1000
144 #define RX_RUNT_ENBL 0x2000
145 #define RX_EXTRA_DATA_ENBL 0x4000
146
147 /* PP_RxCTL - Receive Control bit definition - Read/write */
148 #define RX_IA_HASH_ACCEPT 0x0040
149 #define RX_PROM_ACCEPT 0x0080
150 #define RX_OK_ACCEPT 0x0100
151 #define RX_MULTCAST_ACCEPT 0x0200
152 #define RX_IA_ACCEPT 0x0400
153 #define RX_BROADCAST_ACCEPT 0x0800
154 #define RX_BAD_CRC_ACCEPT 0x1000
155 #define RX_RUNT_ACCEPT 0x2000
156 #define RX_EXTRA_DATA_ACCEPT 0x4000
157 #define RX_ALL_ACCEPT (RX_PROM_ACCEPT | RX_BAD_CRC_ACCEPT | \
158 RX_RUNT_ACCEPT | RX_EXTRA_DATA_ACCEPT)
159 /*
160 * Default receive mode - individually addressed, broadcast, and error free
161 */
162 #define RX_DEF_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
163
164 /*
165 * PP_TxCFG - Transmit Configuration Interrupt Mask
166 * bit definition - Read/write
167 */
168 #define TX_LOST_CRS_ENBL 0x0040
169 #define TX_SQE_ERROR_ENBL 0x0080
170 #define TX_OK_ENBL 0x0100
171 #define TX_LATE_COL_ENBL 0x0200
172 #define TX_JBR_ENBL 0x0400
173 #define TX_ANY_COL_ENBL 0x0800
174 #define TX_16_COL_ENBL 0x8000
175
176 /*
177 * PP_TxCMD - Transmit Command bit definition - Read-only
178 */
179 #define TX_START_4_BYTES 0x0000
180 #define TX_START_64_BYTES 0x0040
181 #define TX_START_128_BYTES 0x0080
182 #define TX_START_ALL_BYTES 0x00C0
183 #define TX_FORCE 0x0100
184 #define TX_ONE_COL 0x0200
185 #define TX_TWO_PART_DEFF_DISABLE 0x0400
186 #define TX_NO_CRC 0x1000
187 #define TX_RUNT 0x2000
188
189 /*
190 * PP_BufCFG - Buffer Configuration Interrupt Mask
191 * bit definition - Read/write
192 */
193 #define GENERATE_SW_INTERRUPT 0x0040
194 #define RX_DMA_ENBL 0x0080
195 #define READY_FOR_TX_ENBL 0x0100
196 #define TX_UNDERRUN_ENBL 0x0200
197 #define RX_MISS_ENBL 0x0400
198 #define RX_128_BYTE_ENBL 0x0800
199 #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
200 #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
201 #define RX_DEST_MATCH_ENBL 0x8000
202
203 /*
204 * PP_LineCTL - Line Control bit definition - Read/write
205 */
206 #define SERIAL_RX_ON 0x0040
207 #define SERIAL_TX_ON 0x0080
208 #define AUI_ONLY 0x0100
209 #define AUTO_AUI_10BASET 0x0200
210 #define MODIFIED_BACKOFF 0x0800
211 #define NO_AUTO_POLARITY 0x1000
212 #define TWO_PART_DEFDIS 0x2000
213 #define LOW_RX_SQUELCH 0x4000
214
215 /*
216 * PP_SelfCTL - Software Self Control bit definition - Read/write
217 */
218 #define POWER_ON_RESET 0x0040
219 #define SW_STOP 0x0100
220 #define SLEEP_ON 0x0200
221 #define AUTO_WAKEUP 0x0400
222 #define HCB0_ENBL 0x1000
223 #define HCB1_ENBL 0x2000
224 #define HCB0 0x4000
225 #define HCB1 0x8000
226
227 /*
228 * PP_BusCTL - ISA Bus Control bit definition - Read/write
229 */
230 #define RESET_RX_DMA 0x0040
231 #define MEMORY_ON 0x0400
232 #define DMA_BURST_MODE 0x0800
233 #define IO_CHANNEL_READY_ON 0x1000
234 #define RX_DMA_SIZE_64Ks 0x2000
235 #define ENABLE_IRQ 0x8000
236
237 /*
238 * PP_TestCTL - Test Control bit definition - Read/write
239 */
240 #define LINK_OFF 0x0080
241 #define ENDEC_LOOPBACK 0x0200
242 #define AUI_LOOPBACK 0x0400
243 #define BACKOFF_OFF 0x0800
244 #define FAST_TEST 0x8000
245
246 /*
247 * PP_RxEvent - Receive Event Bit definition - Read-only
248 */
249 #define RX_IA_HASHED 0x0040
250 #define RX_DRIBBLE 0x0080
251 #define RX_OK 0x0100
252 #define RX_HASHED 0x0200
253 #define RX_IA 0x0400
254 #define RX_BROADCAST 0x0800
255 #define RX_CRC_ERROR 0x1000
256 #define RX_RUNT 0x2000
257 #define RX_EXTRA_DATA 0x4000
258
259 #define HASH_INDEX_MASK 0x0FC00
260
261 /*
262 * PP_TxEvent - Transmit Event Bit definition - Read-only
263 */
264 #define TX_LOST_CRS 0x0040
265 #define TX_SQE_ERROR 0x0080
266 #define TX_OK 0x0100
267 #define TX_LATE_COL 0x0200
268 #define TX_JBR 0x0400
269 #define TX_16_COL 0x8000
270 #define TX_SEND_OK_BITS (TX_OK | TX_LOST_CRS)
271 #define TX_COL_COUNT_MASK 0x7800
272
273 /*
274 * PP_BufEvent - Buffer Event Bit definition - Read-only
275 */
276 #define SW_INTERRUPT 0x0040
277 #define RX_DMA 0x0080
278 #define READY_FOR_TX 0x0100
279 #define TX_UNDERRUN 0x0200
280 #define RX_MISS 0x0400
281 #define RX_128_BYTE 0x0800
282 #define TX_COL_OVRFLW 0x1000
283 #define RX_MISS_OVRFLW 0x2000
284 #define RX_DEST_MATCH 0x8000
285
286 /*
287 * PP_LineST - Ethernet Line Status bit definition - Read-only
288 */
289 #define LINK_OK 0x0080
290 #define AUI_ON 0x0100
291 #define TENBASET_ON 0x0200
292 #define POLARITY_OK 0x1000
293 #define CRS_OK 0x4000
294
295 /*
296 * PP_SelfST - Chip Software Status bit definition
297 */
298 #define ACTIVE_33V 0x0040
299 #define INIT_DONE 0x0080
300 #define SI_BUSY 0x0100
301 #define EEPROM_PRESENT 0x0200
302 #define EEPROM_OK 0x0400
303 #define EL_PRESENT 0x0800
304 #define EE_SIZE_64 0x1000
305
306 /*
307 * PP_BusST - ISA Bus Status bit definition
308 */
309 #define TX_BID_ERROR 0x0080
310 #define READY_FOR_TX_NOW 0x0100
311
312 /*
313 * PP_AutoNegCTL - Auto Negotiation Control bit definition
314 */
315 #define RE_NEG_NOW 0x0040
316 #define ALLOW_FDX 0x0080
317 #define AUTO_NEG_ENABLE 0x0100
318 #define NLP_ENABLE 0x0200
319 #define FORCE_FDX 0x8000
320 #define AUTO_NEG_BITS (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE)
321 #define AUTO_NEG_MASK (FORCE_FDX | NLP_ENABLE | AUTO_NEG_ENABLE | \
322 ALLOW_FDX | RE_NEG_NOW)
323
324 /*
325 * PP_AutoNegST - Auto Negotiation Status bit definition
326 */
327 #define AUTO_NEG_BUSY 0x0080
328 #define FLP_LINK 0x0100
329 #define FLP_LINK_GOOD 0x0800
330 #define LINK_FAULT 0x1000
331 #define HDX_ACTIVE 0x4000
332 #define FDX_ACTIVE 0x8000
333
334 /*
335 * The following block defines the ISQ event types
336 */
337 #define ISQ_RECEIVER_EVENT 0x04
338 #define ISQ_TRANSMITTER_EVENT 0x08
339 #define ISQ_BUFFER_EVENT 0x0c
340 #define ISQ_RX_MISS_EVENT 0x10
341 #define ISQ_TX_COL_EVENT 0x12
342
343 #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
344 #define ISQ_HIST 16 /* small history buffer */
345 #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
346
347 #define TXRXBUFSIZE 0x0600
348 #define RXDMABUFSIZE 0x8000
349 #define RXDMASIZE 0x4000
350 #define TXRX_LENGTH_MASK 0x07FF
351
352 /* rx options bits */
353 #define RCV_WITH_RXON 1 /* Set SerRx ON */
354 #define RCV_COUNTS 2 /* Use Framecnt1 */
355 #define RCV_PONG 4 /* Pong respondent */
356 #define RCV_DONG 8 /* Dong operation */
357 #define RCV_POLLING 0x10 /* Poll RxEvent */
358 #define RCV_ISQ 0x20 /* Use ISQ, int */
359 #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
360 #define RCV_DMA 0x200 /* Set RxDMA only */
361 #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
362 #define RCV_FIXED_DATA 0x800 /* Every frame same */
363 #define RCV_IO 0x1000 /* Use ISA IO only */
364 #define RCV_MEMORY 0x2000 /* Use ISA Memory */
365
366 #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
367 #define PKT_START PP_TxFrame /* Start of packet RAM */
368
369 #define RX_FRAME_PORT 0x0000
370 #define TX_FRAME_PORT RX_FRAME_PORT
371 #define TX_CMD_PORT 0x0004
372 #define TX_CS8900_NOW 0x0000 /* Tx packet after 5 bytes copied */
373 #define TX_CS8900_AFTER_381 0x0020 /* Tx packet after 381 bytes copied */
374 #define TX_CS8900_AFTER_ALL 0x0060 /* Tx packet after all bytes copied */
375 #define TX_CS8920_NOW 0x0000 /* Tx packet after 5 bytes copied */
376 #define TX_CS8920_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
377 #define TX_CS8920_AFTER_1021 0x0080 /* Tx packet after1021 bytes copied */
378 #define TX_CS8920_AFTER_ALL 0x00C0 /* Tx packet after all bytes copied */
379 #define TX_LEN_PORT 0x0006
380 #define ISQ_PORT 0x0008
381 #define ADD_PORT 0x000A
382 #define DATA_PORT 0x000C
383
384 #define EEPROM_WRITE_EN 0x00F0
385 #define EEPROM_WRITE_DIS 0x0000
386 #define EEPROM_WRITE_CMD 0x0100
387 #define EEPROM_READ_CMD 0x0200
388
389 /* Receive Header
390 * Description of header of each packet in receive area of memory
391 */
392 #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
393 #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
394 #define RBUF_LEN_LOW 2 /* Length of received data - low byte */
395 #define RBUF_LEN_HI 3 /* Length of received data - high byte */
396 #define RBUF_HEAD_LEN 4 /* Length of this header */
397
398 #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
399 #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
400
401 /* for bios scan */
402 /* */
403 #ifdef CSDEBUG
404 /* use these values for debugging bios scan */
405 #define BIOS_START_SEG 0x00000
406 #define BIOS_OFFSET_INC 0x0010
407 #else
408 #define BIOS_START_SEG 0x0c000
409 #define BIOS_OFFSET_INC 0x0200
410 #endif
411
412 #define BIOS_LAST_OFFSET 0x0fc00
413
414 /*
415 * Word offsets into the EEPROM configuration buffer
416 */
417 #define ISA_CNF_OFFSET 0x3
418 #define INT_NO_MASK 0x000F
419 #define DMA_NO_MASK 0x0070
420 #define USE_SA 0x0080
421 #define IOCHRDY_ENABLE 0x0100
422 #define ISA_DMA_SIZE 0x0200 /* 0 16k 1 64k */
423 #define ISA_AUTO_RxDMA 0x0400
424 #define ISA_RxDMA 0x0800
425 #define DMA_BURST 0x1000
426 #define STREAM_TRANSFER 0x2000
427 #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
428 #define BOOT_PROM_FLAG 0x4000
429 #define MEMORY_MODE 0x8000
430
431 #define PACKET_PAGE_BASE (ISA_CNF_OFFSET + 1)
432 #define BOOT_ROM_BASE (ISA_CNF_OFFSET + 2)
433 #define BOOT_PROM_MASK (ISA_CNF_OFFSET + 3)
434
435 #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 4) /* 8900 eeprom */
436 #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 4) /* 8920 eeprom */
437 /*
438 * the assumption here is that the bits in the eeprom are generally
439 * in the same position as those in the autonegctl register.
440 * Of course the IMM bit is not in that register so it must be
441 * masked out
442 */
443 #define EE_FORCE_FDX 0x8000
444 #define EE_NLP_ENABLE 0x0200
445 #define EE_AUTO_NEG_ENABLE 0x0100
446 #define EE_ALLOW_FDX 0x0080
447 #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX | EE_NLP_ENABLE | \
448 EE_AUTO_NEG_ENABLE | EE_ALLOW_FDX)
449 #define IMM_BIT 0x0040 /* ignore missing media */
450
451 #define ADAPTER_CNF_OFFSET (ISA_CNF_OFFSET + 5)
452 #define A_CNF_MEDIA 0x0007
453 #define A_CNF_10B_T 0x0001
454 #define A_CNF_AUI 0x0002
455 #define A_CNF_10B_2 0x0004
456 #define A_CNF_MEDIA_TYPE 0x0060
457 #define A_CNF_MEDIA_AUTO 0x0000
458 #define A_CNF_MEDIA_10B_T 0x0020
459 #define A_CNF_MEDIA_AUI 0x0040
460 #define A_CNF_MEDIA_10B_2 0x0060
461 #define A_CNF_DC_DC_POLARITY 0x0080
462 #define A_CNF_WAKE_ENABLED 0x0100
463 #define A_CNF_WAKE_CFG 0x0200
464 #define A_CNF_CAN_WAKE 0x0400
465 #define A_CNF_OPT_FLAGS 0x1800 /* 00 server, 01 DOS 10 multi-user */
466 #define A_CNF_NO_AUTO_POLARITY 0x2000
467 #define A_CNF_LOW_RX_SQUELCH 0x4000
468 #define A_CNF_EXTND_10B_2 0x8000
469
470 #define MFG_DATE_OFFSET (ISA_CNF_OFFSET + 8)
471
472 #define PACKET_PAGE_OFFSET 0x8
473
474 /* DMA controller registers */
475 #define DMA_BASE 0x00 /* DMA controller base */
476 #define DMA_BASE_2 0x0C0 /* DMA controller base */
477
478 #define DMA_STAT 0x0D0 /* DMA controller status register */
479 #define DMA_MASK 0x0D4 /* DMA controller mask register */
480 #define DMA_MODE 0x0D6 /* DMA controller mode register */
481 #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
482
483 /* DMA data */
484 #define DMA_DISABLE 0x04 /* Disable channel n */
485 #define DMA_ENABLE 0x00 /* Enable channel n */
486 /* Demand transfers, incr. address, auto init, writes, ch. n */
487 #define DMA_RX_MODE 0x14
488 /* Demand transfers, incr. address, auto init, reads, ch. n */
489 #define DMA_TX_MODE 0x18
490
491 #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
492
493 #define CS8900 0x0000
494 #define CS8920 0x4000
495 #define CS8920M 0x6000
496 #define REVISON_BITS 0x1F00
497 #define EEVER_NUMBER 0x12
498 #define CHKSUM_LEN 0x14
499 #define CHKSUM_VAL 0x0000
500 #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
501 #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
502 #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
503 #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
504 #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
505
506 #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
507
508 #define PNP_ADD_PORT 0x0279
509 #define PNP_WRITE_PORT 0x0A79
510
511 #define GET_PNP_ISA_STRUCT 0x40
512 #define PNP_ISA_STRUCT_LEN 0x06
513 #define PNP_CSN_CNT_OFF 0x01
514 #define PNP_RD_PORT_OFF 0x02
515 #define PNP_FUNCTION_OK 0x00
516 #define PNP_WAKE 0x03
517 #define PNP_RSRC_DATA 0x04
518 #define PNP_RSRC_READY 0x01
519 #define PNP_STATUS 0x05
520 #define PNP_ACTIVATE 0x30
521 #define PNP_CNF_IO_H 0x60
522 #define PNP_CNF_IO_L 0x61
523 #define PNP_CNF_INT 0x70
524 #define PNP_CNF_DMA 0x74
525 #define PNP_CNF_MEM 0x48
526
527 #define BIT0 1
528 #define BIT15 0x8000
529
530 #define CS_DUPLEX_AUTO 0
531 #define CS_DUPLEX_FULL 1
532 #define CS_DUPLEX_HALF 2
533
534 /*
535 * It would appear that for pccards (well, the IBM EtherJet PCMCIA card) that
536 * are connected to card bus bridges there's a problem. For reading the
537 * value back you have to go into 8 bit mode. The Linux driver also uses
538 * this trick. This may be a bug in the card and how it handles fast 16-bit
539 * read after a write.
540 */
541 #define HACK_FOR_CARDBUS_BRIDGE_PROBLEM
542 #ifdef HACK_FOR_CARDBUS_BRIDGE_PROBLEM
543 static __inline uint16_t
cs_inw(struct cs_softc * sc,int off)544 cs_inw(struct cs_softc *sc, int off)
545 {
546 if (off & 1)
547 device_printf(sc->dev, "BUG: inw to an odd address.\n");
548 return ((bus_read_1(sc->port_res, off)) |
549 (bus_read_1(sc->port_res, off + 1) << 8));
550 }
551 #else
552 static __inline uint16_t
cs_inw(struct cs_softc * sc,int off)553 cs_inw(struct cs_softc *sc, int off)
554 {
555 return (bus_read_2(sc->port_res, off));
556 }
557 #endif
558
559 static __inline void
cs_outw(struct cs_softc * sc,int off,uint16_t val)560 cs_outw(struct cs_softc *sc, int off, uint16_t val)
561 {
562 bus_write_2(sc->port_res, off, val);
563 }
564
565 static __inline uint16_t
cs_readreg(struct cs_softc * sc,uint16_t port)566 cs_readreg(struct cs_softc *sc, uint16_t port)
567 {
568 cs_outw(sc, ADD_PORT, port);
569 return (cs_inw(sc, DATA_PORT));
570 }
571 static __inline void
cs_writereg(struct cs_softc * sc,uint16_t port,uint16_t val)572 cs_writereg(struct cs_softc *sc, uint16_t port, uint16_t val)
573 {
574 cs_outw(sc, ADD_PORT, port);
575 cs_outw(sc, DATA_PORT, val);
576 }
577
578 static __inline void
reset_chip(struct cs_softc * sc)579 reset_chip(struct cs_softc *sc)
580 {
581 cs_writereg(sc, PP_SelfCTL,
582 cs_readreg(sc, PP_SelfCTL) | POWER_ON_RESET);
583 }
584
585 #define cs_duplex_full(sc) \
586 (cs_writereg(sc, PP_AutoNegCTL, FORCE_FDX))
587
588 #define cs_duplex_half(sc) \
589 (cs_writereg(sc, PP_AutoNegCTL, NLP_ENABLE))
590
591