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Searched refs:PLL (Results 1 – 25 of 39) sorted by relevance

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/freebsd-12.1/sys/arm/nvidia/tegra124/
H A Dtegra124_clk_pll.c119 #define PLL(_id, cname, pname) \ macro
221 PLL(TEGRA124_CLK_PLL_M, "pllM_out0", "osc_div_clk"),
232 PLL(TEGRA124_CLK_PLL_X, "pllX_out", "osc_div_clk"),
245 PLL(TEGRA124_CLK_PLL_C, "pllC_out0", "osc_div_clk"),
303 PLL(TEGRA124_CLK_PLL_A, "pllA_out", "pllP_out1"),
313 PLL(TEGRA124_CLK_PLL_U, "pllU_out", "osc_div_clk"),
324 PLL(TEGRA124_CLK_PLL_D, "pllD_out", "osc_div_clk"),
334 PLL(TEGRA124_CLK_PLL_D2, "pllD2_out", "pllD2_src"),
347 PLL(0, "pllREFE_out", "osc_div_clk"),
360 PLL(TEGRA124_CLK_PLL_E, "pllE_out0", "pllE_src"),
[all …]
/freebsd-12.1/sys/gnu/dts/arm/
H A Dvexpress-v2p-ca15-tc1.dts146 /* CPU PLL reference clock */
164 /* HDLCD PLL reference clock */
182 /* SYS PLL reference clock */
191 /* DDR2 PLL reference clock */
H A Dvexpress-v2p-ca15_a7.dts257 /* A15 PLL 0 reference clock */
266 /* A15 PLL 1 reference clock */
275 /* A7 PLL 0 reference clock */
284 /* A7 PLL 1 reference clock */
302 /* HDLCD PLL reference clock */
320 /* SYS PLL reference clock */
329 /* DDR2 PLL reference clock */
H A Ddra62x-clocks.dtsi22 /* Compared to dm814x, dra62x has interconnect clocks on isp PLL */
H A Dam3874-iceboard.dts361 /* The PLL doesn't react well to the SPI controller reset, so
376 DM814X_IOPAD(0x0950, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS1 as GPIO */
377 DM814X_IOPAD(0x0818, PIN_INPUT_PULLUP | 0x80) /* PLL SPI CS2 as GPIO */
H A Dbcm-cygnus-clock.dtsi44 /* Cygnus ARM PLL */
H A Dstih416-clock.dtsi498 * A9 PLL
726 * DDR PLL
742 * GPU PLL
H A Darmada-370-xp.dtsi308 /* 2 GHz fixed main PLL */
H A Dstih418-clock.dtsi34 * A9 PLL.
H A Dstih407-clock.dtsi31 * A9 PLL.
H A Dstih410-clock.dtsi34 * A9 PLL.
H A Darm-realview-eb.dtsi110 /* FIXME: this actually hangs off the PLL clocks */
H A Darmada-39x.dtsi544 /* 1 GHz fixed main PLL */
H A Dstih415-clock.dtsi495 * A9 PLL
H A Darmada-375.dtsi33 /* 1 GHz fixed main PLL */
H A Darm-realview-pbx.dtsi125 /* FIXME: this actually hangs off the PLL clocks */
/freebsd-12.1/sys/mips/ingenic/
H A Djz4780_clock.c82 #define PLL(_id, cname, pname, reg) { \ macro
140 PLL(JZ4780_CLK_APLL, "apll", "ext", JZ_CPAPCR),
141 PLL(JZ4780_CLK_MPLL, "mpll", "ext", JZ_CPMPCR),
142 PLL(JZ4780_CLK_EPLL, "epll", "ext", JZ_CPEPCR),
143 PLL(JZ4780_CLK_VPLL, "vpll", "ext", JZ_CPVPCR),
/freebsd-12.1/contrib/ntp/html/hints/
H A Dlinux1 The kernel PLL interface is broken, I know.
H A Dsolaris.xtra.40958495 Synopsis: time_constant value >6 with PLL in use leads to integer divide
30 is done without the PLL algorithm in the kernel.
/freebsd-12.1/sys/dev/bhnd/cores/pmu/
H A Dbhnd_pmu_if.m203 * Return the current value of a PMU PLL control register.
219 * Write @p value with @p mask to a PMU PLL control register.
/freebsd-12.1/sys/dev/bktr/
H A DCHANGELOG.TXT218 with single crystal PLL configuration
246 PAL/SECAM boards will use PLL mode.
407 Tidy up a few tables with tabs and PLL selection code.
408 Restore Video Highway Xtreme PLL code.
420 Make PLL mode the default for Bt878 chips. This means PAL
/freebsd-12.1/sys/mips/conf/
H A DTL-WR1043NDv2.hints103 # if_arge thus wont change the PLL configuration
H A DDIR-655A1.hints113 # if_arge thus wont change the PLL configuration
H A DAP135.hints88 # if_arge thus wont change the PLL configuration
H A DTL-ARCHERC7V2.hints105 # if_arge thus wont change the PLL configuration

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