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Searched refs:OutputArg (Results 1 – 25 of 57) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsCCState.h38 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
43 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
60 PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
90 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
105 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
131 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
141 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, in CheckReturn()
H A DMipsCCState.cpp100 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForF128()
122 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForVectorFloat()
124 ISD::OutputArg Out = Outs[i]; in PreAnalyzeReturnForVectorFloat()
133 const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeCallOperands()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DTargetCallingConv.h175 struct OutputArg { struct
191 OutputArg() = default; argument
192 OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed, in OutputArg() function
H A DCallingConvLower.h301 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
307 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
312 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
322 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeArguments()
/freebsd-12.1/contrib/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h138 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<ISD::OutputArg> &Outs,
172 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h91 const SmallVectorImpl<ISD::OutputArg> &Outs,
101 const SmallVectorImpl<ISD::OutputArg> &Outs,
104 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h156 const SmallVectorImpl<ISD::OutputArg> &Outs,
220 const SmallVectorImpl<ISD::OutputArg> &Outs,
227 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
/freebsd-12.1/contrib/llvm/lib/Target/ARC/
H A DARCISelLowering.h106 const SmallVectorImpl<ISD::OutputArg> &Outs,
112 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h152 const SmallVectorImpl<ISD::OutputArg> &Outs,
157 const SmallVectorImpl<ISD::OutputArg> &Outs,
162 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h117 const SmallVectorImpl<ISD::OutputArg> &Outs,
145 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h78 const SmallVectorImpl<ISD::OutputArg> &Outs,
81 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DWebAssemblyISelLowering.cpp630 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; in LowerCall()
634 const ISD::OutputArg &Out = Outs[i]; in LowerCall()
673 const ISD::OutputArg &Out = Outs[I]; in LowerCall()
762 const SmallVectorImpl<ISD::OutputArg> &Outs, in CanLowerReturn()
770 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
782 for (const ISD::OutputArg &Out : Outs) { in LowerReturn()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DCallingConvLower.cpp106 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn()
120 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
138 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h972 const SmallVectorImpl<ISD::OutputArg> &Outs,
1052 const SmallVectorImpl<ISD::OutputArg> &Outs,
1056 const SmallVectorImpl<ISD::OutputArg> &Outs,
1085 const SmallVectorImpl<ISD::OutputArg> &Outs,
1094 const SmallVectorImpl<ISD::OutputArg> &Outs,
1103 const SmallVectorImpl<ISD::OutputArg> &Outs,
H A DPPCCCState.cpp18 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeCallOperands()
H A DPPCCCState.h23 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
/freebsd-12.1/contrib/llvm/lib/Target/AVR/
H A DAVRISelLowering.h149 const SmallVectorImpl<ISD::OutputArg> &Outs,
153 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h261 const SmallVectorImpl<ISD::OutputArg> &Outs,
265 const SmallVectorImpl<ISD::OutputArg> &Outs,
288 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h59 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
H A DSystemZISelLowering.h489 const SmallVectorImpl<ISD::OutputArg> &Outs,
492 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h494 const SmallVectorImpl<ISD::OutputArg> &,
499 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFISelLowering.h97 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h116 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
216 const SmallVectorImpl<ISD::OutputArg> &Outs,
220 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h565 const SmallVectorImpl<ISD::OutputArg> &Outs,
582 const SmallVectorImpl<ISD::OutputArg> &Outs,
586 const SmallVectorImpl<ISD::OutputArg> &Outs,
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.h763 const SmallVectorImpl<ISD::OutputArg> &Outs,
770 const SmallVectorImpl<ISD::OutputArg> &Outs,
774 const SmallVectorImpl<ISD::OutputArg> &Outs,

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