| /freebsd-12.1/contrib/llvm/tools/llvm-readobj/ |
| H A D | ARMWinEHPrinter.h | 38 bool opcode_0xxxxxxx(const uint8_t *Opcodes, unsigned &Offset,
40 bool opcode_10Lxxxxx(const uint8_t *Opcodes, unsigned &Offset,
42 bool opcode_1100xxxx(const uint8_t *Opcodes, unsigned &Offset,
44 bool opcode_11010Lxx(const uint8_t *Opcodes, unsigned &Offset,
46 bool opcode_11011Lxx(const uint8_t *Opcodes, unsigned &Offset,
48 bool opcode_11100xxx(const uint8_t *Opcodes, unsigned &Offset,
50 bool opcode_111010xx(const uint8_t *Opcodes, unsigned &Offset,
52 bool opcode_1110110L(const uint8_t *Opcodes, unsigned &Offset,
54 bool opcode_11101110(const uint8_t *Opcodes, unsigned &Offset,
56 bool opcode_11101111(const uint8_t *Opcodes, unsigned &Offset,
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| H A D | ARMEHABIPrinter.h | 101 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_00xxxxxx()
107 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_01xxxxxx()
113 uint8_t Opcode0 = Opcodes[OI++ ^ 3]; in Decode_1000iiii_iiiiiiii()
126 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011101()
131 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10011111()
136 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_1001nnnn()
141 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10100nnn()
148 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10101nnn()
155 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110000()
172 uint8_t Opcode = Opcodes[OI++ ^ 3]; in Decode_10110010_uleb128()
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| H A D | ARMWinEHPrinter.cpp | 781 void Decoder::decodeOpcodes(ArrayRef<uint8_t> Opcodes, unsigned Offset, in decodeOpcodes() argument
786 for (unsigned OI = Offset, OE = Opcodes.size(); !Terminated && OI < OE; ) { in decodeOpcodes()
791 Opcodes.data()[OI]); in decodeOpcodes()
796 if ((Opcodes[OI] & DecodeRing[DI].Mask) == DecodeRing[DI].Value) { in decodeOpcodes()
799 Opcodes[OI]); in decodeOpcodes()
804 (this->*DecodeRing[DI].Routine)(Opcodes.data(), OI, 0, Prologue); in decodeOpcodes()
877 ListScope Opcodes(SW, "Opcodes"); in dumpXDataRecord() local
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrFMA3Info.h | 31 uint16_t Opcodes[3]; member
61 return Opcodes[Form132]; in get132Opcode()
66 return Opcodes[Form213]; in get213Opcode()
71 return Opcodes[Form231]; in get231Opcode()
91 return Opcodes[0] < RHS.Opcodes[0];
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| H A D | X86InstrFMA3Info.cpp | 165 return Group.Opcodes[FormIndex] < Opcode; in getFMA3Group()
167 assert(I != Table.end() && I->Opcodes[FormIndex] == Opcode && in getFMA3Group()
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| /freebsd-12.1/contrib/llvm/lib/Object/ |
| H A D | MachOObjectFile.cpp | 3040 Ptr = Opcodes.begin(); in moveToFirst()
3045 Ptr = Opcodes.end(); in moveToEnd()
3351 if (Ptr > Opcodes.end()) in readULEB128()
3352 Ptr = Opcodes.end(); in readULEB128()
3392 assert(Opcodes == Other.Opcodes && "compare iterators of different files"); in operator ==()
3425 Ptr = Opcodes.begin(); in moveToFirst()
3430 Ptr = Opcodes.end(); in moveToEnd()
3901 if (Ptr > Opcodes.end()) in readULEB128()
3902 Ptr = Opcodes.end(); in readULEB128()
3911 Ptr = Opcodes.end(); in readSLEB128()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMUnwindOpAsm.h | 63 void EmitRaw(const SmallVectorImpl<uint8_t> &Opcodes) { in EmitRaw() argument
64 Ops.insert(Ops.end(), Opcodes.begin(), Opcodes.end()); in EmitRaw()
65 OpBegins.push_back(OpBegins.back() + Opcodes.size()); in EmitRaw()
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| H A D | ARMELFStreamer.cpp | 709 SmallVector<uint8_t, 64> Opcodes; member in __anonb90111790111::ARMELFStreamer
1253 Opcodes.clear(); in EHReset()
1298 assert(Opcodes.size() == 4u && in emitFnEnd()
1300 uint64_t Intval = Opcodes[0] | in emitFnEnd()
1301 Opcodes[1] << 8 | in emitFnEnd()
1302 Opcodes[2] << 16 | in emitFnEnd()
1303 Opcodes[3] << 24; in emitFnEnd()
1304 EmitIntValue(Intval, Opcodes.size()); in emitFnEnd()
1376 assert((Opcodes.size() % 4) == 0 && in FlushUnwindOpcodes()
1379 uint64_t Intval = Opcodes[I] | in FlushUnwindOpcodes()
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | PredicateExpander.cpp | 119 const RecVec &Opcodes) { in expandCheckOpcode() argument
120 assert(!Opcodes.empty() && "Expected at least one opcode to check!"); in expandCheckOpcode()
123 if (Opcodes.size() == 1) { in expandCheckOpcode()
125 expandCheckOpcode(OS, Opcodes[0]); in expandCheckOpcode()
132 for (const Record *Rec : Opcodes) { in expandCheckOpcode()
149 const RecVec &Opcodes) { in expandCheckPseudo() argument
153 expandCheckOpcode(OS, Opcodes); in expandCheckPseudo()
231 const RecVec &Opcodes = Rec->getValueAsListOfDefs("Opcodes"); in expandOpcodeSwitchCase() local
232 for (const Record *Opcode : Opcodes) { in expandOpcodeSwitchCase()
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| H A D | CodeGenSchedule.h | 352 std::vector<const Record *> Opcodes; variable
362 assert(std::find(Opcodes.begin(), Opcodes.end(), Opcode) == Opcodes.end() && in addOpcode()
364 Opcodes.push_back(Opcode); in addOpcode()
367 ArrayRef<const Record *> getOpcodes() const { return Opcodes; } in getOpcodes()
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| H A D | FixedLenDecoderEmitter.cpp | 344 const std::vector<unsigned> &Opcodes; member in __anonc01b33bf0511::FilterChooser
533 Owner->insnWithID(Insn, Owner->Opcodes[i]); in Filter()
542 LastOpcFiltered = Owner->Opcodes[i]; in Filter()
1438 unsigned numInstructions = Opcodes.size(); in filterProcessor()
1451 for (unsigned i = 0; i < Opcodes.size(); ++i) { in filterProcessor()
1457 insnWithID(Insn, Opcodes[i]); in filterProcessor()
1501 insnWithID(insn, Opcodes[InsnIndex]); in filterProcessor()
1667 unsigned Num = Opcodes.size(); in doFilter()
1693 if (Opcodes.size() == 1) { in emitTableEntries()
1697 emitSingletonTableEntry(TableInfo, Opcodes[0]); in emitTableEntries()
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| H A D | PredicateExpander.h | 73 void expandCheckPseudo(raw_ostream &OS, const RecVec &Opcodes);
74 void expandCheckOpcode(raw_ostream &OS, const RecVec &Opcodes);
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| H A D | DAGISelMatcherOpt.cpp | 390 StringSet<> Opcodes; in FactorNodes() local
394 assert(Opcodes.insert(COM->getOpcode().getEnumName()).second && in FactorNodes()
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| H A D | CodeGenSchedule.cpp | 260 RecVec Opcodes = R->getValueAsListOfDefs("Opcodes"); in checkSTIPredicates() local
261 if (Opcodes.empty()) { in checkSTIPredicates()
307 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate() local
308 for (const Record *Opcode : Opcodes) { in processSTIPredicate()
339 RecVec Opcodes = EC->getValueAsListOfDefs("Opcodes"); in processSTIPredicate() local
349 for (const Record *Opcode : Opcodes) { in processSTIPredicate()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstructionSelector.cpp | 102 } const Opcodes; member in __anon2f75b15d0111::ARMInstructionSelector
146 TRI(*STI.getRegisterInfo()), TM(TM), RBI(RBI), STI(STI), Opcodes(STI), in ARMInstructionSelector()
299 return Size == 8 ? Opcodes.SEXT8 : Opcodes.SEXT16; in selectSimpleExtOpc()
302 return Size == 8 ? Opcodes.ZEXT8 : Opcodes.ZEXT16; in selectSimpleExtOpc()
316 return isStore ? Opcodes.STORE8 : Opcodes.LOAD8; in selectLoadStoreOpCode()
318 return isStore ? Opcodes.STORE16 : Opcodes.LOAD16; in selectLoadStoreOpCode()
320 return isStore ? Opcodes.STORE32 : Opcodes.LOAD32; in selectLoadStoreOpCode()
763 I.setDesc(TII.get(Opcodes.AND)); in select()
775 BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.RSB)) in select()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/ |
| H A D | LegalizerInfo.cpp | 299 std::initializer_list<unsigned> Opcodes) { in getActionDefinitionsBuilder() argument
300 unsigned Representative = *Opcodes.begin(); in getActionDefinitionsBuilder()
302 assert(!empty(Opcodes) && Opcodes.begin() + 1 != Opcodes.end() && in getActionDefinitionsBuilder()
305 for (auto I = Opcodes.begin() + 1, E = Opcodes.end(); I != E; ++I) in getActionDefinitionsBuilder()
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetInstrPredicate.td | 161 // Check that the instruction opcode is one of the opcodes in set `Opcodes`.
165 class CheckOpcode<list<Instruction> Opcodes> : MCInstPredicate {
166 list<Instruction> ValidOpcodes = Opcodes;
170 // `Opcodes`. This check is always expanded to "false" if we are generating
172 class CheckPseudo<list<Instruction> Opcodes> : CheckOpcode<Opcodes>;
211 list<Instruction> Opcodes = opcodes;
279 list<Instruction> Opcodes = opcodes;
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| /freebsd-12.1/contrib/binutils/gas/doc/ |
| H A D | c-ia64.texi | 24 * IA-64 Opcodes:: Opcodes
173 @node IA-64 Opcodes
174 @section Opcodes
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| H A D | c-avr.texi | 21 * AVR Opcodes:: Opcodes
212 @node AVR Opcodes
213 @section Opcodes
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| H A D | c-arc.texi | 24 * ARC Opcodes:: Opcodes
325 @node ARC Opcodes
326 @section Opcodes
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| H A D | c-sh.texi | 15 * SH Opcodes:: Opcodes
210 @node SH Opcodes
211 @section Opcodes
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| H A D | c-alpha.texi | 24 * Alpha Opcodes:: Opcodes
458 @node Alpha Opcodes
459 @section Opcodes
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| /freebsd-12.1/contrib/llvm/include/llvm/Object/ |
| H A D | MachO.h | 195 ArrayRef<uint8_t> Opcodes; variable
219 ArrayRef<uint8_t> Opcodes, bool is64Bit, MachOBindEntry::Kind);
247 ArrayRef<uint8_t> Opcodes; variable
397 ArrayRef<uint8_t> Opcodes,
412 ArrayRef<uint8_t> Opcodes,
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 247 std::pair<unsigned, unsigned> Opcodes = getMFHiLoOpc(Src); in expandCopy() local
249 if (!Opcodes.first) in expandCopy()
252 return expandCopyACC(MBB, I, Opcodes.first, Opcodes.second); in expandCopy()
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| /freebsd-12.1/contrib/llvm/lib/ObjectYAML/ |
| H A D | DWARFYAML.cpp | 164 IO.mapRequired("Opcodes", LineTable.Opcodes); in mapping()
|