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Searched refs:OpNode (Results 1 – 25 of 35) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64InstrFormats.td6270 asm, ".8b", OpNode, v8i8>;
7515 (OpNode (v4f16 V64:$Rn),
7542 (OpNode (v2f32 V64:$Rn),
7747 (OpNode (v4i16 V64:$Rn),
7760 (OpNode (v8i16 V128:$Rn),
7773 (OpNode (v2i32 V64:$Rn),
7785 (OpNode (v4i32 V128:$Rn),
7805 (OpNode FPR32Op:$Rn,
7821 (OpNode (v4i16 V64:$Rn),
7834 (OpNode (v8i16 V128:$Rn),
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86InstrAVX512.td4042 def : Pat<(_.VT (OpNode _.RC:$src0,
4053 def : Pat<(_.VT (OpNode _.RC:$src0,
6727 (_.VT (OpNode
6736 (_.VT (OpNode
6926 (OpNode _.RC:$src2,
7000 (_.VT (OpNode _.RC:$src2,
7471 (OpNode _.RC:$src2,
9678 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
9702 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
9714 defm NAME: avx512_trunc<opc, OpcodeStr, InVecNode, OpNode, OpNode,
[all …]
H A DX86InstrFMA.td179 SDPatternOperator OpNode,
194 (OpNode RC:$src2, RC:$src1, (load addr:$src3)))]>,
243 SDNode OpNode, RegisterClass RC,
246 x86memop, RC, OpNode, sched>;
248 x86memop, RC, OpNode, sched>;
250 x86memop, RC, OpNode, sched>;
403 [(set RC:$dst, (OpNode RC:$src1, RC:$src2,
462 multiclass fma4p<bits<8> opc, string OpcodeStr, SDNode OpNode,
478 [(set VR128:$dst, (OpNode VR128:$src1, VR128:$src2,
505 [(set VR256:$dst, (OpNode VR256:$src1, VR256:$src2,
[all …]
H A DX86InstrFPStack.td127 multiclass FPBinary_rr<SDNode OpNode> {
131 [(set RFP32:$dst, (OpNode RFP32:$src1, RFP32:$src2))]>;
133 [(set RFP64:$dst, (OpNode RFP64:$src1, RFP64:$src2))]>;
135 [(set RFP80:$dst, (OpNode RFP80:$src1, RFP80:$src2))]>;
140 multiclass FPBinary<SDNode OpNode, Format fp, string asmstring,
148 (OpNode RFP32:$src1, (loadf32 addr:$src2))),
155 (OpNode RFP64:$src1, (loadf64 addr:$src2))),
300 multiclass FPUnary<SDNode OpNode, Format fp, string asmstring> {
302 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
304 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
[all …]
H A DX86InstrXOP.td95 multiclass xop3op<bits<8> opc, string OpcodeStr, SDNode OpNode,
107 (vt128 (OpNode (vt128 VR128:$src1),
114 (vt128 (OpNode (vt128 (load addr:$src1)),
141 multiclass xop3opimm<bits<8> opc, string OpcodeStr, SDNode OpNode,
147 (vt128 (OpNode (vt128 VR128:$src1), imm:$src2)))]>,
153 (vt128 (OpNode (vt128 (load addr:$src1)), imm:$src2)))]>,
262 (vt128 (OpNode (vt128 VR128:$src1),
282 def : Pat<(OpNode (load addr:$src2),
297 multiclass xop4op<bits<8> opc, string OpcodeStr, SDNode OpNode,
304 (vt128 (OpNode (vt128 VR128:$src1), (vt128 VR128:$src2),
[all …]
H A DX86InstrSSE.td30 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))], d>,
174 multiclass sse12_move_rr<SDNode OpNode, ValueType vt,
1834 [(set RC:$dst, (OpNode (VT RC:$src1),
2173 (vt (OpNode RC:$src1,
3060 def : Pat<(ScalarVT (OpNode (load addr:$src))),
3720 [(set RC:$dst, (DstVT (OpNode RC:$src1,
3886 (vt128 (OpNode (memop addr:$src1),
3925 (OutVT (OpNode (ArgVT RC:$src1),
8332 (vt128 (OpNode VR128:$src1,
8346 (vt256 (OpNode VR256:$src1,
[all …]
H A DX86InstrCMovSetCC.td81 multiclass SETCC<bits<8> opc, string Mnemonic, PatLeaf OpNode> {
85 [(set GR8:$dst, (X86setcc OpNode, EFLAGS))]>,
89 [(store (X86setcc OpNode, EFLAGS), addr:$dst)]>,
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.h85 bool SelectADDRri_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
87 bool SelectADDRri(SDNode *OpNode, SDValue Addr, SDValue &Base,
89 bool SelectADDRri64(SDNode *OpNode, SDValue Addr, SDValue &Base,
91 bool SelectADDRsi_imp(SDNode *OpNode, SDValue Addr, SDValue &Base,
93 bool SelectADDRsi(SDNode *OpNode, SDValue Addr, SDValue &Base,
95 bool SelectADDRsi64(SDNode *OpNode, SDValue Addr, SDValue &Base,
H A DNVPTXInstrInfo.td159 multiclass I3<string OpcStr, SDNode OpNode> {
208 multiclass F3<string OpcStr, SDNode OpNode> {
382 multiclass F2<string OpcStr, SDNode OpNode> {
499 multiclass ADD_SUB_i1<SDNode OpNode> {
1691 : ISET_FORMAT<OpNode, Mode,
1703 : ISET_FORMAT<OpNode, Mode,
2058 [(OpNode (i32 4))]>;
2061 [(OpNode (i32 5))]>;
2065 [(OpNode (i32 6))]>;
2069 [(OpNode (i32 7))]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsDSPInstrInfo.td277 list<dag> Pattern = [(set ROD:$rd, (OpNode ROS:$rs))];
288 list<dag> Pattern = [(OpNode ROS:$rs, ROT:$rt)];
322 list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
327 class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
333 list<dag> Pattern = [(set RO:$rd, (OpNode immPat:$imm))];
360 class LX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
458 list<dag> Pattern = [(OpNode GPR32Opnd:$rs, immZExt10:$mask)];
474 class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
502 list<dag> Pattern = [(set GPR32Opnd:$rd, (OpNode RO:$ac))];
1439 DSPPat<(i32 (OpNode GPR32:$rs, ACC64DSP:$ac)),
[all …]
H A DMipsInstrFPU.td110 SDPatternOperator OpNode= null_frag> :
113 [(set RC:$fd, (OpNode RC:$fs, RC:$ft))], Itin, FrmFR, opstr>,
119 SDPatternOperator OpNode = null_frag> {
129 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
134 SDPatternOperator OpNode= null_frag> :
143 SDPatternOperator OpNode= null_frag> {
199 SDPatternOperator OpNode = null_frag> :
206 SDPatternOperator OpNode = null_frag> :
225 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
255 SDPatternOperator OpNode = null_frag> :
[all …]
H A DMipsMSAInstrInfo.td1294 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1305 list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
1312 [(set RCWD:$wd, (OpNode RCWS:$fs))]> {
1322 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
1402 MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
1460 list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
1495 [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
2310 class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2647 class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
2654 list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
[all …]
H A DMicroMipsDSPInstrInfo.td180 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
186 list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
216 class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
222 list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
253 class SHLLV_R3_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
258 list<dag> Pattern = [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))];
285 class EXT_MM_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
292 class EXT_MM_1R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
337 class MFHI_MM_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
342 list<dag> Pattern = [(set GPR32Opnd:$rs, (OpNode RO:$ac))];
H A DMicroMipsInstrFPU.td15 SDPatternOperator OpNode = null_frag> {
16 def _D32_MM : MMRel, ADDS_FT<opstr, AFGR64Opnd, Itin, IsComm, OpNode>,
21 def _D64_MM : ADDS_FT<opstr, FGR64Opnd, Itin, IsComm, OpNode>, FGR_64 {
112 SDPatternOperator OpNode = null_frag> {
113 def _D32_MM : MMRel, ABSS_FT<opstr, AFGR64Opnd, AFGR64Opnd, Itin, OpNode>,
118 def _D64_MM : ABSS_FT<opstr, FGR64Opnd, FGR64Opnd, Itin, OpNode>,
H A DMipsInstrInfo.td1362 SDPatternOperator OpNode = null_frag>:
1375 SDPatternOperator OpNode = null_frag> :
1429 SDPatternOperator OpNode = null_frag,
1442 LoadMemory<opstr, RO, mem, OpNode, Itin, Addr>;
1445 SDPatternOperator OpNode = null_frag,
1457 StoreMemory<opstr, RO, MO, OpNode, Itin, Addr>;
1474 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
1481 SDPatternOperator OpNode= null_frag> :
1490 SDPatternOperator OpNode= null_frag> :
1500 SDPatternOperator OpNode= null_frag> :
[all …]
H A DMipsCondMov.td37 SDPatternOperator OpNode = null_frag> :
40 [(set RC:$rd, (OpNode RC:$rs, FCCRegsOpnd:$fcc, RC:$F))],
47 SDPatternOperator OpNode = null_frag> :
50 [(set RC:$fd, (OpNode RC:$fs, FCCRegsOpnd:$fcc, RC:$F))],
H A DMicroMipsInstrInfo.td210 class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
214 [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))],
223 class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO,
227 [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> {
296 [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI, opstr> {
304 SDPatternOperator OpNode = null_frag> :
318 SDPatternOperator OpNode = null_frag> :
321 [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
336 class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode,
346 SDPatternOperator OpNode, InstrItinClass Itin,
[all …]
H A DMips16InstrInfo.td1306 class ArithLogicU_pat<PatFrag OpNode, Instruction I> :
1307 Mips16Pat<(OpNode CPU16Regs:$r),
1313 class ArithLogic16_pat<SDNode OpNode, Instruction I> :
1314 Mips16Pat<(OpNode CPU16Regs:$l, CPU16Regs:$r),
1327 Mips16Pat<(OpNode CPU16Regs:$in, imm_type:$imm),
1336 class shift_rotate_reg16_pat<SDNode OpNode, Instruction I> :
1337 Mips16Pat<(OpNode CPU16Regs:$r, CPU16Regs:$ra),
1344 class LoadM16_pat<PatFrag OpNode, Instruction I, ComplexPattern Addr> :
1345 Mips16Pat<(OpNode Addr:$addr), (I Addr:$addr)>;
1361 class UncondBranch16_pat<SDNode OpNode, Instruction I>:
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/BPF/
H A DBPFInstrInfo.td212 multiclass ALU<BPFArithOp Opc, string OpcodeStr, SDNode OpNode> {
217 [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>;
227 [(set GPR32:$dst, (OpNode i32:$src2, i32:$src))]>;
358 class STOREi64<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
359 : STORE<Opc, OpcodeStr, [(OpNode i64:$src, ADDRri:$addr)]>;
549 class XADD<BPFWidthModifer SizeOp, string OpcodeStr, PatFrag OpNode>
554 [(set GPR:$dst, (OpNode ADDRri:$addr, GPR:$val))]> {
606 [(set R0, (OpNode GPR:$skb, i64immSExt32:$imm))]> {
618 [(set R0, (OpNode GPR:$skb, GPR:$val))]> {
669 class STOREi32<BPFWidthModifer Opc, string OpcodeStr, PatFrag OpNode>
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.td273 multiclass ALUbase<bits<3> subOp, string AsmStr, SDNode OpNode,
288 multiclass ALUarith<bits<3> subOp, string AsmStr, SDNode OpNode,
301 defm I_ : ALUbase<subOp, AsmStr, OpNode, LoExt, HiExt,
480 class LoadRR<string OpcString, PatFrag OpNode, ValueType Ty>
483 [(set (Ty GPR:$Rd), (OpNode ADDRrr:$src))]>,
496 class LoadRI<string OpcString, PatFrag OpNode, ValueType Ty>
499 [(set (Ty GPR:$Rd), (OpNode ADDRri:$src))]>,
598 class StoreRR<string OpcString, PatFrag OpNode, ValueType Ty>
601 [(OpNode (Ty GPR:$Rd), ADDRrr:$dst)]>,
615 class StoreRI<string OpcString, PatFrag OpNode, ValueType Ty>
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMInstrNEON.td2987 (OpNode (TyQ QPR:$src1),
2999 (OpNode (TyQ QPR:$src1),
3008 SDNode OpNode>
3082 (TyQ (OpNode (TyD DPR:$Vn),
3091 (TyQ (OpNode (TyD DPR:$Vn),
3234 SDPatternOperator OpNode>
3410 SDNode OpNode> {
3665 SDNode OpNode> {
7025 : NEONFPPat<(f32 (OpNode SPR:$a)),
7069 : NEONFPPat<(f32 (OpNode GPR:$a)),
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.td217 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
231 SDNode OpNode> {
240 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
243 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
252 SDNode OpNode> {
263 SDNode OpNode> {
272 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
275 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
295 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
297 [(OpNode immU6:$a)]>;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoD.td201 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
202 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;
204 class PatFpr64Fpr64DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
205 : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2, 0b111)>;
H A DRISCVInstrInfoF.td241 class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>
242 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2)>;
244 class PatFpr32Fpr32DynFrm<SDPatternOperator OpNode, RVInstRFrm Inst>
245 : Pat<(OpNode FPR32:$rs1, FPR32:$rs2), (Inst $rs1, $rs2, 0b111)>;
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.td309 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
315 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))],
343 [(set Ty:$dst, (OpNode ADDRrr:$addr))],
348 [(set Ty:$dst, (OpNode ADDRri:$addr))],
354 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
364 Load<OpcStr, Op3Val, OpNode, RC, Ty, itin> {
365 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
385 [(OpNode Ty:$rd, ADDRrr:$addr)],
390 [(OpNode Ty:$rd, ADDRri:$addr)],
407 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
[all …]

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