Searched refs:OpEntry (Results 1 – 2 of 2) sorted by relevance
1708 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in selectDivRem() local1720 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy), in selectDivRem()1724 if (OpEntry.OpSignExtend) { in selectDivRem()1725 if (OpEntry.IsOpSigned) in selectDivRem()1727 TII.get(OpEntry.OpSignExtend)); in selectDivRem()1754 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem)) in selectDivRem()1766 OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) { in selectDivRem()1788 .addReg(OpEntry.DivRemResultReg); in selectDivRem()
1950 const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; in X86SelectDivRem() local1960 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); in X86SelectDivRem()1962 if (OpEntry.OpSignExtend) { in X86SelectDivRem()1963 if (OpEntry.IsOpSigned) in X86SelectDivRem()1965 TII.get(OpEntry.OpSignExtend)); in X86SelectDivRem()1991 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); in X86SelectDivRem()2003 OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { in X86SelectDivRem()2021 .addReg(OpEntry.DivRemResultReg); in X86SelectDivRem()