Searched refs:Offset0 (Results 1 – 8 of 8) sorted by relevance
| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 125 unsigned Offset0; member 313 if (CI.Offset0 == CI.Offset1) in offsetsCanBeCombined() 320 unsigned EltOffset0 = CI.Offset0 / CI.EltSize; in offsetsCanBeCombined() 337 CI.Offset0 = EltOffset0 / 64; in offsetsCanBeCombined() 345 CI.Offset0 = EltOffset0; in offsetsCanBeCombined() 352 CI.BaseOff = std::min(CI.Offset0, CI.Offset1); in offsetsCanBeCombined() 362 CI.Offset0 = EltOffset0 - CI.BaseOff / CI.EltSize; in offsetsCanBeCombined() 634 CI.Offset0 &= 0xffff; in findMatchingInst() 691 unsigned NewOffset0 = CI.Offset0; in mergeRead2Pair() 792 unsigned NewOffset0 = CI.Offset0; in mergeWrite2Pair() [all …]
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| H A D | AMDGPUISelDAGToDAG.cpp | 118 bool SelectDS64Bit4ByteAligned(SDValue Ptr, SDValue &Base, SDValue &Offset0, 914 SDValue &Offset0, in SelectDS64Bit4ByteAligned() argument 927 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); in SelectDS64Bit4ByteAligned() 956 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); in SelectDS64Bit4ByteAligned() 973 Offset0 = CurDAG->getTargetConstant(DWordOffset0, DL, MVT::i8); in SelectDS64Bit4ByteAligned() 982 Offset0 = CurDAG->getTargetConstant(0, DL, MVT::i8); in SelectDS64Bit4ByteAligned()
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| H A D | SIInstrInfo.cpp | 152 int64_t &Offset0, in areLoadsFromSameBasePtr() argument 214 Offset0 = Load0Offset->getZExtValue(); in areLoadsFromSameBasePtr() 248 Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue(); in areLoadsFromSameBasePtr() 294 uint8_t Offset0 = Offset0Imm->getImm(); in getMemOperandWithOffset() local 297 if (Offset1 > Offset0 && Offset1 - Offset0 == 1) { in getMemOperandWithOffset() 314 Offset = EltSize * Offset0; in getMemOperandWithOffset() 482 assert(Offset1 > Offset0 && in shouldScheduleLoadsNear() 488 return (NumLoads <= 16 && (Offset1 - Offset0) < 64); in shouldScheduleLoadsNear() 2178 int64_t Offset0, Offset1; in checkInstOffsetsDoNotOverlap() local 2180 if (getMemOperandWithOffset(MIa, BaseOp0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap() [all …]
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| H A D | SIInstrInfo.h | 183 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
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| H A D | SIInstrInfo.td | 731 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
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| H A D | SIISelLowering.cpp | 5487 unsigned Offset0 = OrderedCountIndex << 2; in LowerINTRINSIC_W_CHAIN() local 5490 unsigned Offset = Offset0 | (Offset1 << 8); in LowerINTRINSIC_W_CHAIN()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 279 int64_t Offset0; in apply() local 281 MachineOperand *BaseOp0 = HII.getBaseAndOffset(L0, Offset0, Size0); in apply() 300 if (((Offset0 ^ Offset1) & 0x18) != 0) in apply()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 12771 const APInt &Offset0 = CN->getAPIntValue(); in CombineToPreIndexedLoadStore() local 12781 APInt CNV = Offset0; in CombineToPreIndexedLoadStore()
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