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Searched refs:NumLanes (Results 1 – 14 of 14) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.cpp151 unsigned NumLanes = Size / 128; in DecodePSHUFMask() local
152 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodePSHUFMask()
153 unsigned NumLaneElts = NumElts / NumLanes; in DecodePSHUFMask()
229 if (NumLanes == 0) NumLanes = 1; // Handle MMX in DecodeUNPCKHMask()
230 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKHMask()
248 if (NumLanes == 0 ) NumLanes = 1; // Handle MMX in DecodeUNPCKLMask()
249 unsigned NumLaneElts = NumElts / NumLanes; in DecodeUNPCKLMask()
496 unsigned NumLanes = VecSize / 128; in DecodeVPERMILPMask() local
497 unsigned NumEltsPerLane = NumElts / NumLanes; in DecodeVPERMILPMask()
518 unsigned NumLanes = VecSize / 128; in DecodeVPERMIL2PMask() local
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/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86MCInstLower.cpp2061 int NumLanes = 1; in EmitInstruction() local
2064 case X86::VBROADCASTF128: NumLanes = 2; break; in EmitInstruction()
2065 case X86::VBROADCASTI128: NumLanes = 2; break; in EmitInstruction()
2066 case X86::VBROADCASTF32X4Z256rm: NumLanes = 2; break; in EmitInstruction()
2067 case X86::VBROADCASTF32X4rm: NumLanes = 4; break; in EmitInstruction()
2068 case X86::VBROADCASTF32X8rm: NumLanes = 2; break; in EmitInstruction()
2069 case X86::VBROADCASTF64X2Z128rm: NumLanes = 2; break; in EmitInstruction()
2070 case X86::VBROADCASTF64X2rm: NumLanes = 4; break; in EmitInstruction()
2071 case X86::VBROADCASTF64X4rm: NumLanes = 2; break; in EmitInstruction()
2086 for (int l = 0; l != NumLanes; ++l) { in EmitInstruction()
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H A DX86InterleavedAccess.cpp473 unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1); in DecodePALIGNRMask() local
474 unsigned NumLaneElts = NumElts / NumLanes; in DecodePALIGNRMask()
H A DX86ISelLowering.cpp6049 int NumLanes = VT.getSizeInBits() / 128; in getPackDemandedElts() local
6052 int NumEltsPerLane = NumElts / NumLanes; in getPackDemandedElts()
10518 int NumLanes = VT.getSizeInBits() / 128; in lowerVectorShuffleAsUNPCKAndPermute() local
10519 int NumLaneElts = NumElts / NumLanes; in lowerVectorShuffleAsUNPCKAndPermute()
10589 int NumLanes = VT.getSizeInBits() / 128; in lowerVectorShuffleAsByteRotateAndPermute() local
10591 int NumEltsPerLane = NumElts / NumLanes; in lowerVectorShuffleAsByteRotateAndPermute()
11334 int NumLanes = Bits / 128; in lowerVectorShuffleAsZeroOrAnyExtend() local
13920 for (int i = 0; i != NumLanes; ++i) { in lowerVectorShuffleAsLanePermuteAndPermute()
14108 int NumLanes = Size / LaneSize; in lowerVectorShuffleByMerging128BitLanes() local
14411 int NumLaneElts = NumElts / NumLanes; in lowerShuffleAsRepeatedMaskAndLanePermute()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIMachineFunctionInfo.cpp261 int NumLanes = Size / 4; in allocateSGPRSpillToVGPR() local
267 for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) { in allocateSGPRSpillToVGPR()
/freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/
H A DInstCombineSimplifyDemanded.cpp1572 unsigned NumLanes = Ty0->getPrimitiveSizeInBits() / 128; in SimplifyDemandedVectorElts() local
1573 unsigned VWidthPerLane = VWidth / NumLanes; in SimplifyDemandedVectorElts()
1574 unsigned InnerVWidthPerLane = InnerVWidth / NumLanes; in SimplifyDemandedVectorElts()
1582 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in SimplifyDemandedVectorElts()
1597 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in SimplifyDemandedVectorElts()
H A DInstCombineCalls.cpp536 unsigned NumLanes = ResTy->getPrimitiveSizeInBits() / 128; in simplifyX86pack() local
541 unsigned NumDstEltsPerLane = NumDstElts / NumLanes; in simplifyX86pack()
542 unsigned NumSrcEltsPerLane = NumSrcElts / NumLanes; in simplifyX86pack()
554 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) { in simplifyX86pack()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/InstPrinter/
H A DAArch64InstPrinter.h150 template <unsigned NumLanes, char LaneKind>
H A DAArch64InstPrinter.cpp1305 template <unsigned NumLanes, char LaneKind>
1310 if (NumLanes) in printTypedVectorList()
1311 Suffix += itostr(NumLanes) + LaneKind; in printTypedVectorList()
/freebsd-12.1/contrib/llvm/tools/clang/utils/TableGen/
H A DNeonEmitter.cpp726 unsigned NumLanes; in fromTypedefName() local
727 Name.substr(0, I).getAsInteger(10, NumLanes); in fromTypedefName()
729 T.Bitwidth = T.ElementBitwidth * NumLanes; in fromTypedefName()
/freebsd-12.1/contrib/llvm/lib/IR/
H A DAutoUpgrade.cpp2126 unsigned NumLanes = VT->getPrimitiveSizeInBits() / 128; in UpgradeIntrinsicCall() local
2128 unsigned ControlBitsMask = NumLanes - 1; in UpgradeIntrinsicCall()
2129 unsigned NumControlBits = NumLanes / 2; in UpgradeIntrinsicCall()
2132 for (unsigned l = 0; l != NumLanes; ++l) { in UpgradeIntrinsicCall()
2135 if (l >= NumLanes / 2) in UpgradeIntrinsicCall()
2136 LaneMask += NumLanes; in UpgradeIntrinsicCall()
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGBuiltin.cpp10282 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
10283 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
10309 unsigned NumLanes = Ty->getPrimitiveSizeInBits() / 128; in EmitX86BuiltinExpr() local
10310 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
10415 unsigned NumLanes = Ty->getPrimitiveSizeInBits() == 512 ? 4 : 2; in EmitX86BuiltinExpr() local
10416 unsigned NumLaneElts = NumElts / NumLanes; in EmitX86BuiltinExpr()
10420 unsigned Index = (Imm % NumLanes) * NumLaneElts; in EmitX86BuiltinExpr()
10421 Imm /= NumLanes; // Discard the bits we just used. in EmitX86BuiltinExpr()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp12112 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVCVTCombine() local
12113 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVCVTCombine()
12132 ISD::INTRINSIC_WO_CHAIN, dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVCVTCombine()
12170 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in PerformVDIVCombine() local
12171 if (FloatBits != 32 || IntBits > 32 || NumLanes > 4) { in PerformVDIVCombine()
12190 dl, NumLanes == 2 ? MVT::v2i32 : MVT::v4i32, in PerformVDIVCombine()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp9123 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFpToIntCombine() local
9124 switch (NumLanes) { in performFpToIntCombine()
9196 unsigned NumLanes = Op.getValueType().getVectorNumElements(); in performFDivCombine() local
9197 switch (NumLanes) { in performFDivCombine()