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Searched refs:NewOpcode (Results 1 – 25 of 26) sorted by relevance

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/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonCFGOptimizer.cpp85 int NewOpcode = 0; in InvertAndChangeJumpTarget() local
88 NewOpcode = Hexagon::J2_jumpf; in InvertAndChangeJumpTarget()
91 NewOpcode = Hexagon::J2_jumpt; in InvertAndChangeJumpTarget()
94 NewOpcode = Hexagon::J2_jumpfnewpt; in InvertAndChangeJumpTarget()
97 NewOpcode = Hexagon::J2_jumptnewpt; in InvertAndChangeJumpTarget()
103 MI.setDesc(TII->get(NewOpcode)); in InvertAndChangeJumpTarget()
H A DHexagonVLIWPacketizer.cpp454 int NewOpcode; in promoteToDotNew() local
456 NewOpcode = HII->getDotNewPredOp(MI, MBPI); in promoteToDotNew()
458 NewOpcode = HII->getDotNewOp(MI); in promoteToDotNew()
459 MI.setDesc(HII->get(NewOpcode)); in promoteToDotNew()
464 int NewOpcode = HII->getDotOldOp(MI); in demoteToDotOld() local
465 MI.setDesc(HII->get(NewOpcode)); in demoteToDotOld()
883 int NewOpcode = HII->getDotNewOp(MI); in canPromoteToDotNew() local
884 const MCInstrDesc &D = HII->get(NewOpcode); in canPromoteToDotNew()
H A DHexagonInstrInfo.cpp1491 unsigned NewOpcode = getInvertedPredicatedOpcode(opcode); in reverseBranchCondition() local
1492 Cond[0].setImm(NewOpcode); in reverseBranchCondition()
3623 int NewOpcode = Hexagon::getPredNewOpcode(MI.getOpcode()); in getDotNewPredOp() local
3624 if (NewOpcode >= 0) in getDotNewPredOp()
3625 return NewOpcode; in getDotNewPredOp()
4328 unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode()); in invertAndChangeJumpTarget() local
4337 NewOpcode = reversePrediction(NewOpcode); in invertAndChangeJumpTarget()
4339 MI.setDesc(get(NewOpcode)); in invertAndChangeJumpTarget()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreRegisterInfo.cpp138 int NewOpcode; in InsertSPImmInst() local
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; in InsertSPImmInst()
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6; in InsertSPImmInst()
147 BuildMI(MBB, II, dl, TII.get(NewOpcode)) in InsertSPImmInst()
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6; in InsertSPImmInst()
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg) in InsertSPImmInst()
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DAMDILCFGStructurizer.cpp222 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
224 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
227 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
230 MachineBasicBlock::iterator I, int NewOpcode,
459 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrEnd()
466 int NewOpcode, in insertInstrBefore() argument
469 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL); in insertInstrBefore()
479 MachineBasicBlock::iterator I, int NewOpcode) { in insertInstrBefore() argument
491 MachineBasicBlock::iterator I, int NewOpcode, const DebugLoc &DL) { in insertCondBranchBefore() argument
495 MachineInstr *NewMI = MF->CreateMachineInstr(TII->get(NewOpcode), DL); in insertCondBranchBefore()
[all …]
H A DSIInstrInfo.cpp4171 unsigned NewOpcode = getVALUOp(Inst); in moveToVALU() local
4250 NewOpcode = AMDGPU::V_LSHLREV_B32_e64; in moveToVALU()
4256 NewOpcode = AMDGPU::V_ASHRREV_I32_e64; in moveToVALU()
4262 NewOpcode = AMDGPU::V_LSHRREV_B32_e64; in moveToVALU()
4268 NewOpcode = AMDGPU::V_LSHLREV_B64; in moveToVALU()
4274 NewOpcode = AMDGPU::V_ASHRREV_I64; in moveToVALU()
4280 NewOpcode = AMDGPU::V_LSHRREV_B64; in moveToVALU()
4336 if (NewOpcode == AMDGPU::INSTRUCTION_LIST_END) { in moveToVALU()
4344 const MCInstrDesc &NewDesc = get(NewOpcode); in moveToVALU()
H A DSIInstrInfo.h721 unsigned NewOpcode) const;
H A DSIISelLowering.cpp9116 int NewOpcode = in adjustWritemask() local
9118 assert(NewOpcode != -1 && in adjustWritemask()
9119 NewOpcode != static_cast<int>(Node->getMachineOpcode()) && in adjustWritemask()
9137 MachineSDNode *NewNode = DAG.getMachineNode(NewOpcode, SDLoc(Node), in adjustWritemask()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp194 int NewOpcode = -1; in encodeInstruction() local
197 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
198 if (NewOpcode == -1) in encodeInstruction()
199 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6); in encodeInstruction()
202 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips); in encodeInstruction()
205 if (NewOpcode == -1) in encodeInstruction()
206 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp); in encodeInstruction()
208 if (NewOpcode != -1) { in encodeInstruction()
212 Opcode = NewOpcode; in encodeInstruction()
213 TmpInst.setOpcode (NewOpcode); in encodeInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZFrameLowering.cpp495 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue() local
499 if (!NewOpcode) { in emitEpilogue()
504 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset); in emitEpilogue()
505 assert(NewOpcode && "No restore instruction available"); in emitEpilogue()
508 MBBI->setDesc(ZII->get(NewOpcode)); in emitEpilogue()
H A DSystemZInstrInfo.cpp77 unsigned NewOpcode) const { in splitMove()
118 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
119 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
136 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset); in splitAdjDynAlloc() local
137 assert(NewOpcode && "No support for huge argument lists yet"); in splitAdjDynAlloc()
138 MI->setDesc(get(NewOpcode)); in splitAdjDynAlloc()
1033 unsigned NewOpcode; in convertToThreeAddress() local
1035 NewOpcode = SystemZ::RISBG; in convertToThreeAddress()
1038 NewOpcode = SystemZ::RISBGN; in convertToThreeAddress()
1040 NewOpcode = SystemZ::RISBMux; in convertToThreeAddress()
[all …]
H A DSystemZInstrInfo.h149 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp331 int NewOpcode = -1; in convertMIMGInst() local
335 NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), 2); in convertMIMGInst()
339 NewOpcode = AMDGPU::getMaskedMIMGOp(MI.getOpcode(), DstSize); in convertMIMGInst()
340 if (NewOpcode == -1) in convertMIMGInst()
344 auto RCID = MCII->get(NewOpcode).OpInfo[VDataIdx].RegClass; in convertMIMGInst()
360 MI.setOpcode(NewOpcode); in convertMIMGInst()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp361 int NewOpcode; in fixupIncDec() local
365 NewOpcode = isINC ? X86::INC16r : X86::DEC16r; in fixupIncDec()
369 NewOpcode = isINC ? X86::INC32r : X86::DEC32r; in fixupIncDec()
372 NewOpcode = isINC ? X86::INC64r : X86::DEC64r; in fixupIncDec()
377 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode)) in fixupIncDec()
H A DX86MCInstLower.cpp319 unsigned NewOpcode = 0; in SimplifyMOVSX() local
326 NewOpcode = X86::CBW; in SimplifyMOVSX()
330 NewOpcode = X86::CWDE; in SimplifyMOVSX()
334 NewOpcode = X86::CDQE; in SimplifyMOVSX()
338 if (NewOpcode != 0) { in SimplifyMOVSX()
340 Inst.setOpcode(NewOpcode); in SimplifyMOVSX()
H A DX86InstrInfo.cpp3605 unsigned NewOpcode = 0; in optimizeCompareInstr() local
3628 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break; in optimizeCompareInstr()
3629 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break; in optimizeCompareInstr()
3630 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break; in optimizeCompareInstr()
3631 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break; in optimizeCompareInstr()
3632 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break; in optimizeCompareInstr()
3633 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break; in optimizeCompareInstr()
3634 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break; in optimizeCompareInstr()
3644 CmpInstr.setDesc(get(NewOpcode)); in optimizeCompareInstr()
3647 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm || in optimizeCompareInstr()
[all …]
H A DX86ISelLowering.cpp38685 unsigned NewOpcode = 0; in combineFneg() local
38688 case ISD::FMA: NewOpcode = X86ISD::FNMSUB; break; in combineFneg()
38701 if (NewOpcode) in combineFneg()
38702 return DAG.getBitcast(OrigVT, DAG.getNode(NewOpcode, DL, VT, in combineFneg()
39632 return DAG.getNode(NewOpcode, dl, VT, A, B, C, N->getOperand(3)); in combineFMA()
39633 return DAG.getNode(NewOpcode, dl, VT, A, B, C); in combineFMA()
39646 unsigned NewOpcode; in combineFMADDSUB() local
39649 case X86ISD::FMADDSUB: NewOpcode = X86ISD::FMSUBADD; break; in combineFMADDSUB()
39650 case X86ISD::FMADDSUB_RND: NewOpcode = X86ISD::FMSUBADD_RND; break; in combineFMADDSUB()
39651 case X86ISD::FMSUBADD: NewOpcode = X86ISD::FMADDSUB; break; in combineFMADDSUB()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiRegisterInfo.cpp232 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode()); in eliminateFrameIndex() local
237 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode), in eliminateFrameIndex()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp1562 std::string NewOpcode; in ParseInstruction() local
1564 NewOpcode = Name; in ParseInstruction()
1565 NewOpcode += '+'; in ParseInstruction()
1566 Name = NewOpcode; in ParseInstruction()
1569 NewOpcode = Name; in ParseInstruction()
1570 NewOpcode += '-'; in ParseInstruction()
1571 Name = NewOpcode; in ParseInstruction()
1577 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
1585 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. in ParseInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp6206 unsigned NewOpcode; in PeepholePPC64ZExt() local
6211 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break; in PeepholePPC64ZExt()
6212 case PPC::SLW: NewOpcode = PPC::SLW8; break; in PeepholePPC64ZExt()
6213 case PPC::SRW: NewOpcode = PPC::SRW8; break; in PeepholePPC64ZExt()
6214 case PPC::LI: NewOpcode = PPC::LI8; break; in PeepholePPC64ZExt()
6215 case PPC::LIS: NewOpcode = PPC::LIS8; break; in PeepholePPC64ZExt()
6216 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break; in PeepholePPC64ZExt()
6221 case PPC::OR: NewOpcode = PPC::OR8; break; in PeepholePPC64ZExt()
6223 case PPC::ORI: NewOpcode = PPC::ORI8; break; in PeepholePPC64ZExt()
6224 case PPC::ORIS: NewOpcode = PPC::ORIS8; break; in PeepholePPC64ZExt()
[all …]
H A DPPCAsmPrinter.cpp1042 unsigned NewOpcode = in EmitInstruction() local
1046 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
1056 unsigned NewOpcode = in EmitInstruction() local
1062 EmitToStreamer(*OutStreamer, MCInstBuilder(NewOpcode) in EmitInstruction()
H A DPPCRegisterInfo.cpp1007 unsigned NewOpcode = ImmToIdxMap.find(OpC)->second; in eliminateFrameIndex() local
1008 MI.setDesc(TII.get(NewOpcode)); in eliminateFrameIndex()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DInstructionSelectorImpl.h656 int64_t NewOpcode = MatchTable[CurrentIdx++]; in executeMatchTable() local
662 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode)); in executeMatchTable()
666 << NewOpcode << ")\n"); in executeMatchTable()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsDelaySlotFiller.cpp565 unsigned NewOpcode = TII->getEquivalentCompactForm(Branch); in replaceWithCompactBranch() local
566 Branch = TII->genInstrWithNewOpc(NewOpcode, Branch); in replaceWithCompactBranch()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3630 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM; in expandLoadStoreMultiple() local
3644 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6; in expandLoadStoreMultiple()
3646 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM; in expandLoadStoreMultiple()
3649 Inst.setOpcode(NewOpcode); in expandLoadStoreMultiple()

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