Searched refs:MidRegLo (Results 1 – 1 of 1) sorted by relevance
4908 unsigned MidRegLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBFE() local4912 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo) in splitScalar64BitBFE()4919 .addReg(MidRegLo); in splitScalar64BitBFE()4922 .addReg(MidRegLo) in splitScalar64BitBFE()