| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstrBuilder.h | 39 class MCInstrDesc; variable
305 const MCInstrDesc &MCID) { in BuildMI()
368 const MCInstrDesc &MCID) { in BuildMI()
378 const MCInstrDesc &MCID) { in BuildMI()
387 const MCInstrDesc &MCID) { in BuildMI()
397 const MCInstrDesc &MCID) { in BuildMI()
404 const MCInstrDesc &MCID) { in BuildMI()
421 const MCInstrDesc &MCID, bool IsIndirect,
428 const MCInstrDesc &MCID, bool IsIndirect,
437 const MCInstrDesc &MCID, bool IsIndirect,
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| H A D | DFAPacketizer.h | 45 class MCInstrDesc; variable
110 bool canReserveResources(const MCInstrDesc *MID);
114 void reserveResources(const MCInstrDesc *MID);
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| /freebsd-12.1/contrib/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 22 bool MCInstrDesc::getDeprecatedInfo(MCInst &MI, const MCSubtargetInfo &STI, in getDeprecatedInfo()
33 bool MCInstrDesc::mayAffectControlFlow(const MCInst &MI, in mayAffectControlFlow()
45 bool MCInstrDesc::hasImplicitDefOfPhysReg(unsigned Reg, in hasImplicitDefOfPhysReg()
54 bool MCInstrDesc::hasDefOfPhysReg(const MCInst &MI, unsigned Reg, in hasDefOfPhysReg()
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| /freebsd-12.1/contrib/llvm/include/llvm/MC/ |
| H A D | MCInstrInfo.h | 25 const MCInstrDesc *Desc; // Raw array to allow static init'n
33 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
45 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCHazardRecognizers.cpp | 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
67 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
87 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID, in mustComeFirst()
149 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in ShouldPreferAnother()
177 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
284 const MCInstrDesc &MCID = DAG.TII->get(Opcode); in GetInstrType()
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| H A D | PPCFrameLowering.cpp | 776 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8 in emitPrologue()
778 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD in emitPrologue()
780 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU in emitPrologue()
786 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8 in emitPrologue()
788 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitPrologue()
1283 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8 in emitEpilogue()
1285 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD in emitEpilogue()
1289 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8 in emitEpilogue()
1291 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8 in emitEpilogue()
1293 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8 in emitEpilogue()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.h | 26 class MCInstrDesc; variable
53 const MCInstrDesc &II,
68 const MCInstrDesc *II,
79 const MCInstrDesc *II,
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| H A D | InstrEmitter.cpp | 133 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
210 const MCInstrDesc &II, in CreateVirtualRegisters()
315 const MCInstrDesc *II, in AddRegisterOperand()
324 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
386 const MCInstrDesc *II, in AddOperand()
652 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
731 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
790 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_LABEL); in EmitDbgLabel()
829 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
970 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 348 const MCInstrDesc &DefMCID,
352 const MCInstrDesc &DefMCID,
356 const MCInstrDesc &UseMCID,
360 const MCInstrDesc &UseMCID,
364 const MCInstrDesc &DefMCID,
366 const MCInstrDesc &UseMCID,
371 const MCInstrDesc &DefMCID, unsigned DefAdj,
374 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
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| H A D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| H A D | MLxExpansionPass.cpp | 187 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
287 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
288 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
342 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 418 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
421 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
424 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
433 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
465 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) { in getOperandSize()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64SIMDInstrOpt.cpp | 161 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
162 SmallVectorImpl<const MCInstrDesc*> &ReplInstrMCID);
219 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst()
220 SmallVectorImpl<const MCInstrDesc*> &InstDescRepl) { in shouldReplaceInst()
275 const MCInstrDesc* OriginalMCID; in shouldExitEarly()
276 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in shouldExitEarly()
352 const MCInstrDesc *MulMCID, *DupMCID; in optimizeVectElement()
418 SmallVector<const MCInstrDesc*, 2> ReplInstrMCID; in optimizeVectElement()
511 SmallVector<const MCInstrDesc*, MaxNumRepl> ReplInstrMCID; in optimizeLdStInterleave()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | DFAPacketizer.cpp | 130 bool DFAPacketizer::canReserveResources(const MCInstrDesc *MID) { in canReserveResources()
140 void DFAPacketizer::reserveResources(const MCInstrDesc *MID) { in reserveResources()
152 const MCInstrDesc &MID = MI.getDesc(); in canReserveResources()
159 const MCInstrDesc &MID = MI.getDesc(); in reserveResources()
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| H A D | ScoreboardHazardRecognizer.cpp | 123 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
178 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | Utils.h | 29 class MCInstrDesc; variable
62 MachineInstr &InsertPt, const MCInstrDesc &II,
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | Mips16InstrInfo.h | 25 class MCInstrDesc; variable
101 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 89 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
304 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in reportBranchErrors()
315 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkHWLoop()
329 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in checkCOFMax1()
456 MCInstrDesc const &Desc = in checkNewValues()
531 MCInstrDesc const &Desc = HexagonMCInstrInfo::getDesc(MCII, I); in registerProducer()
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| /freebsd-12.1/contrib/llvm/lib/MCA/ |
| H A D | InstrBuilder.cpp | 190 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc, in computeMaxLatency()
205 static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) { in verifyOperands()
236 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateWrites()
406 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode()); in populateReads()
503 const MCInstrDesc &MCDesc = MCII.get(Opcode); in createInstrDescImpl()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86FixupLEAs.cpp | 391 const MCInstrDesc &Desc = MI.getDesc(); in processInstruction()
454 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode)); in processInstructionForSlowLEA()
462 const MCInstrDesc &ADDri = in processInstructionForSlowLEA()
515 const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode)); in processInstrForSlow3OpLEA()
516 const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset)); in processInstrForSlow3OpLEA()
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| H A D | X86OptimizeLEAs.cpp | 337 const MCInstrDesc &Desc = MI.getDesc(); in chooseBestLEA()
439 const MCInstrDesc &Desc = MI.getDesc(); in isReplaceable()
504 const MCInstrDesc &Desc = MI.getDesc(); in removeRedundantAddrCalc()
636 const MCInstrDesc &Desc = MI.getDesc(); in removeRedundantLEAs()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| H A D | SIMCCodeEmitter.cpp | 270 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
347 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getSDWASrcEncoding()
429 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonOptAddrMode.cpp | 127 const MCInstrDesc &MID = MI.getDesc(); in INITIALIZE_PASS_DEPENDENCY()
194 const MCInstrDesc &UseMID = UseMI.getDesc(); in canRemoveAddasl()
357 const MCInstrDesc &MID = MI->getDesc(); in processAddUses()
416 const MCInstrDesc &MID = UseMI->getDesc(); in updateAddUses()
444 const MCInstrDesc &MID = MI.getDesc(); in analyzeUses()
625 const MCInstrDesc &UseMID = UseMI->getDesc(); in changeAddAsl()
672 const MCInstrDesc &MID = UseMI->getDesc(); in xformUseMI()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIFrameLowering.cpp | 384 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); in emitEntryFunctionScratchSetup()
391 const MCInstrDesc &GetPC64 = TII->get(AMDGPU::S_GETPC_B64); in emitEntryFunctionScratchSetup()
419 const MCInstrDesc &LoadDwordX4 = TII->get(AMDGPU::S_LOAD_DWORDX4_IMM); in emitEntryFunctionScratchSetup()
437 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32); in emitEntryFunctionScratchSetup()
449 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64); in emitEntryFunctionScratchSetup()
455 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM); in emitEntryFunctionScratchSetup()
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| /freebsd-12.1/contrib/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrBuilder.h | 31 const MCInstrDesc &MCID = MI->getDesc(); in addFrameReference()
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