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Searched refs:LoadedVT (Results 1 – 6 of 6) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp1358 EVT LoadedVT = LD->getMemoryVT(); in tryARMIndexedLoad() local
1363 if (LoadedVT == MVT::i32 && isPre && in tryARMIndexedLoad()
1367 } else if (LoadedVT == MVT::i32 && !isPre && in tryARMIndexedLoad()
1371 } else if (LoadedVT == MVT::i32 && in tryARMIndexedLoad()
1376 } else if (LoadedVT == MVT::i16 && in tryARMIndexedLoad()
1382 } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { in tryARMIndexedLoad()
1433 EVT LoadedVT = LD->getMemoryVT(); in tryT1IndexedLoad() local
1436 LoadedVT.getSimpleVT().SimpleTy != MVT::i32) in tryT1IndexedLoad()
1464 EVT LoadedVT = LD->getMemoryVT(); in tryT2IndexedLoad() local
1471 switch (LoadedVT.getSimpleVT().SimpleTy) { in tryT2IndexedLoad()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXISelDAGToDAG.cpp843 EVT LoadedVT = LD->getMemoryVT(); in tryLoad() local
850 if (!LoadedVT.isSimple()) in tryLoad()
885 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad()
894 assert(LoadedVT == MVT::v2f16 && "Unexpected vector type"); in tryLoad()
1000 EVT LoadedVT = MemSD->getMemoryVT(); in tryLoadVector() local
1002 if (!LoadedVT.isSimple()) in tryLoadVector()
1023 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp72 EVT LoadedVT = LD->getMemoryVT(); in SelectIndexedLoad() local
79 bool IsValidInc = HII->isValidAutoIncImm(LoadedVT, Inc); in SelectIndexedLoad()
81 assert(LoadedVT.isSimple()); in SelectIndexedLoad()
82 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectIndexedLoad()
153 assert(LoadedVT.getSizeInBits() <= 32); in SelectIndexedLoad()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp4858 EVT LoadedVT = LD->getMemoryVT(); in expandUnalignedLoad() local
4863 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); in expandUnalignedLoad()
4864 if (isTypeLegal(intVT) && isTypeLegal(LoadedVT)) { in expandUnalignedLoad()
4866 LoadedVT.isVector()) { in expandUnalignedLoad()
4878 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); in expandUnalignedLoad()
4879 if (LoadedVT != VT) in expandUnalignedLoad()
4889 unsigned LoadedBytes = LoadedVT.getStoreSize(); in expandUnalignedLoad()
4894 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); in expandUnalignedLoad()
4945 LoadedVT); in expandUnalignedLoad()
4951 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && in expandUnalignedLoad()
[all …]
H A DDAGCombiner.cpp4208 EVT LoadedVT = LoadN->getMemoryVT(); in isAndLoadExtLoad() local
4210 if (ExtVT == LoadedVT && in isAndLoadExtLoad()
4224 if (!LoadedVT.bitsGT(ExtVT) || !ExtVT.isRound()) in isAndLoadExtLoad()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp4436 EVT LoadedVT = LD->getMemoryVT(); in Select() local
4455 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
4456 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
4467 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
4468 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
4492 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); in Select()
4493 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()
4506 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) && in Select()
4508 switch (LoadedVT.getSimpleVT().SimpleTy) { in Select()