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Searched refs:Load0 (Results 1 – 4 of 4) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp151 bool SIInstrInfo::areLoadsFromSameBasePtr(SDNode *Load0, SDNode *Load1, in areLoadsFromSameBasePtr() argument
154 if (!Load0->isMachineOpcode() || !Load1->isMachineOpcode()) in areLoadsFromSameBasePtr()
157 unsigned Opc0 = Load0->getMachineOpcode(); in areLoadsFromSameBasePtr()
167 if (getNumOperandsNoGlue(Load0) != getNumOperandsNoGlue(Load1)) in areLoadsFromSameBasePtr()
171 if (Load0->getOperand(1) != Load1->getOperand(1)) in areLoadsFromSameBasePtr()
175 if (findChainOperand(Load0) != findChainOperand(Load1)) in areLoadsFromSameBasePtr()
199 if (Load0->getOperand(0) != Load1->getOperand(0)) in areLoadsFromSameBasePtr()
203 dyn_cast<ConstantSDNode>(Load0->getOperand(1)); in areLoadsFromSameBasePtr()
211 if (findChainOperand(Load0) != findChainOperand(Load1)) in areLoadsFromSameBasePtr()
224 findChainOperand(Load0) != findChainOperand(Load1) || in areLoadsFromSameBasePtr()
[all …]
H A DSIInstrInfo.h183 bool shouldScheduleLoadsNear(SDNode *Load0, SDNode *Load1, int64_t Offset0,
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp1499 SDValue Load0 = DAG.getLoad(SingleTy, dl, Chain, Base0, MOp0); in SplitHvxMemOp() local
1502 { DAG.getNode(ISD::CONCAT_VECTORS, dl, MemTy, Load0, Load1), in SplitHvxMemOp()
1504 Load0.getValue(1), Load1.getValue(1)) }, dl); in SplitHvxMemOp()
H A DHexagonISelLowering.cpp2683 SDValue Load0 = DAG.getLoad(LoadTy, dl, Chain, Base0, WideMMO); in LowerUnalignedLoad() local
2687 {Load1, Load0, BaseNoOff.getOperand(0)}); in LowerUnalignedLoad()
2689 Load0.getValue(1), Load1.getValue(1)); in LowerUnalignedLoad()