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Searched refs:LSU (Results 1 – 25 of 25) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td84 def : WriteRes<LSU, [ZEC12_LSUnit]>;
128 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
133 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
213 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
303 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
439 def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],
504 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
550 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, NormalGr],
577 def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],
729 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
[all …]
H A DSystemZScheduleZ196.td83 def : WriteRes<LSU, [Z196_LSUnit]>;
123 def : InstRW<[WLat1, FXU3, LSU, GroupAlone2],
127 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
129 def : InstRW<[WLat1, FXU, LSU, GroupAlone],
205 def : InstRW<[WLat2LSU, RegReadAdv, FXU, LSU, EndGroup],
292 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
428 def : InstRW<[WLat6LSU, RegReadAdv, FXU, LSU, NormalGr],
493 def : InstRW<[WLat1LSU, RegReadAdv, FXU, LSU, NormalGr],
565 def : InstRW<[WLat2LSU, WLat2LSU, FXU2, LSU, GroupAlone],
691 def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
[all …]
H A DSystemZScheduleZ13.td89 def : WriteRes<LSU, [Z13_LSUnit]>;
235 def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
237 def : InstRW<[WLat1, FXb, LSU, NormalGr],
329 def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
466 def : InstRW<[WLat6LSU, RegReadAdv, FXa, LSU, NormalGr],
522 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
532 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
578 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
671 def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
697 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZScheduleZ14.td89 def : WriteRes<LSU, [Z14_LSUnit]>;
236 def : InstRW<[WLat2LSU, RegReadAdv, FXa, LSU, NormalGr],
238 def : InstRW<[WLat1, FXb, LSU, NormalGr],
330 def : InstRW<[WLat1LSU, RegReadAdv, FXa, LSU, NormalGr],
467 def : InstRW<[WLat5LSU, RegReadAdv, FXa, LSU, NormalGr],
532 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
542 def : InstRW<[WLat1LSU, RegReadAdv, FXb, LSU, NormalGr],
588 def : InstRW<[WLat2LSU, RegReadAdv, FXb, LSU, NormalGr],
691 def : InstRW<[WLat8, VecDFX, LSU, LSU, GroupAlone], (instregex "CP$")>;
717 def : InstRW<[WLat3, LSU, EndGroup], (instregex "SPM$")>;
[all …]
H A DSystemZSchedule.td23 // A SchedWrite added to other SchedWrites to make LSU latency parameterizable.
30 def "WLat"#L#"LSU" : WriteSequence<[!cast<SchedWrite>("WLat"#L),
44 def "LSU"#Num : SchedWrite;
/freebsd-12.1/contrib/llvm/lib/MCA/
H A DContext.cpp38 auto LSU = llvm::make_unique<LSUnit>(SM, Opts.LoadQueueSize, in createDefaultPipeline() local
40 auto HWS = llvm::make_unique<Scheduler>(SM, *LSU); in createDefaultPipeline()
52 addHardwareUnit(std::move(LSU)); in createDefaultPipeline()
/freebsd-12.1/contrib/llvm/lib/MCA/HardwareUnits/
H A DScheduler.cpp54 switch (LSU.isAvailable(IR)) { in isAvailable()
83 LSU.onInstructionExecuted(IR); in issueInstructionImpl()
173 LSU.onInstructionExecuted(IR); in updateIssuedSet()
218 LSU.dispatch(IR); in dispatch()
243 return IR.getInstruction()->isReady() && (!IsMemOp || LSU.isReady(IR)); in isReady()
/freebsd-12.1/contrib/gcc/config/arm/
H A Darm1026ejs.md48 ;; - A Load-Store Unit (LSU) pipeline.
50 ;; The LSU pipeline has decode, execute, memory, and write stages.
159 ;; LSU instructions require six cycles to execute. They use the ALU
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
181 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
192 ;; stage in the LSU pipeline. That is modeled by keeping the ALU
H A Darm1020e.md48 ;; - A Load-Store Unit (LSU) pipeline.
50 ;; The LSU pipeline has decode, execute, memory, and write stages.
159 ;; LSU instructions require six cycles to execute. They use the ALU
160 ;; pipeline in all but the 5th cycle, and the LSU pipeline in cycles
181 ;; On a LDM/STM operation, the LSU pipeline iterates until all of the
H A Darm1136jfs.md57 ;; - A 4-stage LSU pipeline. It has address generation, data cache (1),
59 ;; including the writeback stage, is independent from the ALU & LSU pipes.)
/freebsd-12.1/contrib/gcc/config/rs6000/
H A D6xx.md28 ;; PPC604 32-bit 2xSCIU, MCIU, LSU, FPU, BPU
29 ;; PPC604e 32-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
31 ;; LSU 2 stage pipelined
40 ;; PPC620 64-bit 2xSCIU, MCIU, LSU, FPU, BPU, CRU
41 ;; PPC630 64-bit 2xSCIU, MCIU, LSU, 2xFPU, BPU, CRU
H A D7450.md31 ;; PPC7450 32-bit 3xIU, MCIU, LSU, SRU, FPU, BPU, 4xVEC
34 ;; LSU 2 stage pipelined
H A D7xx.md28 ;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU
31 ;; LSU 2 stage pipelined
H A Dmpc.md26 ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
H A Drs64.md27 ;; RS64a 64-bit IU, LSU, FPU, BPU
H A D603.md26 ;; PPC603/PPC603e 32-bit IU, LSU, FPU, BPU, SRU
H A D8540.md61 ;; Here we simplified LSU unit description not describing the stages.
/freebsd-12.1/contrib/llvm/include/llvm/MCA/HardwareUnits/
H A DScheduler.h88 LSUnit &LSU; variable
130 : LSU(Lsu), Resources(std::move(RM)) { in Scheduler()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCScheduleP7.td46 // Each LSU pipeline can also execute FX add and logical instructions.
47 // Each LSU pipeline can complete a load or store in one cycle.
49 // Each store is broken into two parts, AGEN goes to the LSU while a
H A DPPCScheduleP8.td28 // 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
258 // op is issued to the LSU, and the data op (register fetch) is issued
395 // to 10 insns per cycle (2-LU, 2-LSU, 2-FXU, 2-FPU, 1-CRU, 1-BRU).
H A DPPCScheduleE500.td26 // 6 pipelined execution units: SU0, SU1, BU, LSU, MU.
32 def E500_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCScheduleE500mc.td26 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
36 def E500mc_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCScheduleE5500.td27 // 6 pipelined execution units: SFX0, SFX1, BU, FPU, LSU, CFX.
39 def E5500_LSU_0 : FuncUnit; // LSU pipeline
H A DPPCInstrInfo.td2403 /// that they will fill slots (which could cause the load of a LSU reject to
/freebsd-12.1/contrib/gcc/
H A DChangeLog-20056787 * config/rs6000/603.md (ppc603-store): Occupy LSU for 2 cycles.