| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/MCTargetDesc/ |
| H A D | AArch64AddressingModes.h | 36 LSR, enumerator
57 case AArch64_AM::LSR: return "lsr"; in getShiftExtendName()
78 case 1: return AArch64_AM::LSR; in getShiftType()
106 case AArch64_AM::LSR: STEnc = 1; break; in getShifterImm()
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.h | 40 LSR, ///< Logical shift right. enumerator
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| H A D | AVRISelLowering.cpp | 257 NODE(LSR); in getTargetNodeName()
324 Opc8 = AVRISD::LSR; in LowerShifts()
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| H A D | AVRInstrInfo.td | 59 def AVRlsr : SDNode<"AVRISD::LSR", SDTIntUnaryOp>;
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| /freebsd-12.1/contrib/llvm/tools/lldb/source/Plugins/Process/Utility/ |
| H A D | ARMUtils.h | 125 static inline uint32_t LSR(const uint32_t value, const uint32_t amount, in LSR() function
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/Utils/ |
| H A D | AArch64BaseInfo.h | 404 LSR, enumerator
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedPredicates.td | 50 def CheckShiftLSR : CheckImmOperand_s<3, "AArch64_AM::LSR">;
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| H A D | AArch64ISelDAGToDAG.cpp | 332 return AArch64_AM::LSR; in getShiftTypeForNode()
1907 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) { in getUsefulBitsFromOrWithShiftedReg()
2369 SDNode *LSR = CurDAG->getMachineNode( in tryBitfieldInsertOpFromOr() local
2378 SDValue Ops[] = {Dst, SDValue(LSR, 0), in tryBitfieldInsertOpFromOr()
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| H A D | AArch64FastISel.cpp | 1250 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break; in emitAddSub()
3747 /*IsKill=*/false, AArch64_AM::LSR, 32, in fastLowerIntrinsicCall()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/AsmParser/ |
| H A D | AArch64AsmParser.cpp | 1222 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isShifter()
1314 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isArithmeticShifter()
1325 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR || in isLogicalShifter()
2751 .Case("lsr", AArch64_AM::LSR) in tryParseOptionalShiftExtend()
2774 if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR || in tryParseOptionalShiftExtend()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonConstPropagation.cpp | 2697 LatticeCell LSR; in evaluateHexCondMove() local
2698 if (!evaluate(R, LR, LSR)) in evaluateHexCondMove()
2700 RC.meet(LSR); in evaluateHexCondMove()
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| /freebsd-12.1/secure/lib/libcrypto/arm/ |
| H A D | bsaes-armv7.S | 1434 mov r6, #:lower16:(.LREVM0SR-.LSR)
1437 sub r6, r8, #.LREVM0SR-.LSR @ pass constants
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrThumb.td | 1138 // LSR immediate
1149 // LSR register
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| H A D | ARMScheduleR52.td | 331 (instregex "ASRr", "RORS?r", "LSR", "LSL")>;
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| H A D | ARMScheduleA57.td | 228 // (ASR, LSL, LSR, ROR, RRX)=MOVsi, MVN
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| H A D | ARMInstrInfo.td | 6091 // LSR, ROR, and RRX instructions.
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| /freebsd-12.1/contrib/llvm/lib/Target/ARC/ |
| H A D | ARCInstrInfo.td | 234 defm LSR : ArcBinaryEXT5Inst<0b000001, "lsr">;
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| /freebsd-12.1/contrib/binutils/gas/ |
| H A D | ChangeLog-0001 | 5275 Issue a warning if "ASR #0" or "LSR #0" is used.
|