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Searched refs:LD1 (Results 1 – 7 of 7) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedKryoDetails.td1018 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)$")>;
1024 (instregex "LD1(i8|i16|i32)$")>;
1036 (instregex "LD1(One(v16b|v8h|v4s|v2d)|i64)_POST$")>;
1042 (instregex "LD1(i8|i16|i32)_POST$")>;
H A DAArch64InstrInfo.td1835 // We must do vector loads with LD1 in big-endian.
1848 // We must do vector loads with LD1 in big-endian.
1975 // We must use LD1 to perform vector loads in big-endian.
1994 // We must use LD1 to perform vector loads in big-endian.
5673 defm LD1 : SIMDLd1Multiple<"ld1">;
5766 ValueType VTy, ValueType STy, Instruction LD1>
5769 (LD1 VecListOne128:$Rd, VecIndex:$idx, GPR64sp:$Rn)>;
5780 ValueType VTy, ValueType STy, Instruction LD1>
5784 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
5795 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
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H A DAArch64SchedFalkorDetails.td782 def : InstRW<[FalkorWr_1LD_3cyc, FalkorReadIncLd], (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|…
784 … (instregex "^LD1(i64|Onev(8b|4h|2s|1d|16b|8h|4s|2d))_POST$")>;
H A DAArch64InstrFormats.td9163 // LD1 instructions have extra "1d" variants.
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp9977 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); in CombineConsecutiveLoads() local
9984 std::swap(LD1, LD2); in CombineConsecutiveLoads()
9986 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || in CombineConsecutiveLoads()
9987 LD1->getAddressSpace() != LD2->getAddressSpace()) in CombineConsecutiveLoads()
9989 EVT LD1VT = LD1->getValueType(0); in CombineConsecutiveLoads()
9992 DAG.areNonVolatileConsecutiveLoads(LD2, LD1, LD1Bytes, 1)) { in CombineConsecutiveLoads()
9993 unsigned Align = LD1->getAlignment(); in CombineConsecutiveLoads()
9999 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), LD1->getBasePtr(), in CombineConsecutiveLoads()
10000 LD1->getPointerInfo(), Align); in CombineConsecutiveLoads()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp12093 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(PreviousInput); in combineBVOfConsecutiveLoads() local
12100 if (!isConsecutiveLS(LD2, LD1, ElemSize, 1, DAG)) in combineBVOfConsecutiveLoads()
12102 if (!isConsecutiveLS(LD1, LD2, ElemSize, 1, DAG)) in combineBVOfConsecutiveLoads()
12119 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(FirstLoadOp); in combineBVOfConsecutiveLoads() local
12122 assert(LD1 && "Input needs to be a LoadSDNode."); in combineBVOfConsecutiveLoads()
12123 return DAG.getLoad(N->getValueType(0), dl, LD1->getChain(), in combineBVOfConsecutiveLoads()
12124 LD1->getBasePtr(), LD1->getPointerInfo(), in combineBVOfConsecutiveLoads()
12125 LD1->getAlignment()); in combineBVOfConsecutiveLoads()
/freebsd-12.1/contrib/llvm/tools/clang/include/clang/Basic/
H A Darm_neon.td616 def LD1 : WInst<"vld1", "dc", "dQdPlQPl">;