Home
last modified time | relevance | path

Searched refs:IssueWidth (Results 1 – 25 of 61) sorted by relevance

123

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp75 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()
106 if (IssueWidth == 0) in atIssueLimit()
109 return IssueCount == IssueWidth; in atIssueLimit()
H A DTargetSchedule.cpp72 ResourceLCM = SchedModel.IssueWidth; in init()
78 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCSchedule.cpp107 return ((double)SCDesc.NumMicroOps) / SM.IssueWidth; in getReciprocalThroughput()
120 return 1.0 / IssueWidth; in getReciprocalThroughput()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86PadShortFunction.cpp209 unsigned IssueWidth = TSM.getIssueWidth(); in addPadding() local
211 for (unsigned i = 0, e = IssueWidth * NOOPsToAdd; i != e; ++i) in addPadding()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleM3.td15 let IssueWidth = 1; // Only IT can be dual-issued, so assume single-issue
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DScoreboardHazardRecognizer.h100 unsigned IssueWidth = 0; variable
H A DTargetSchedule.h96 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonScheduleV62.td29 let IssueWidth = 4;
H A DHexagonScheduleV65.td32 let IssueWidth = 4;
H A DHexagonScheduleV66.td32 let IssueWidth = 4;
H A DHexagonScheduleV5.td38 let IssueWidth = 4;
H A DHexagonScheduleV55.td40 let IssueWidth = 4;
H A DHexagonScheduleV60.td73 let IssueWidth = 4;
/freebsd-12.1/contrib/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td40 let IssueWidth = 1;
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCSchedule.h256 unsigned IssueWidth; member
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCScheduleA2.td160 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
H A DPPCScheduleG5.td119 let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
H A DPPCScheduleE500.td272 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
H A DPPCScheduleE500mc.td327 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DSISchedule.td54 let IssueWidth = 1;
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td20 let IssueWidth = 8; // 8 uops are dispatched per cycle.
H A DAArch64SchedKryo.td21 let IssueWidth = 5; // 5-wide issue for expanded uops
/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetItinerary.td90 // global IssueWidth property, which constrains the number of microops
/freebsd-12.1/contrib/llvm/tools/llvm-mca/
H A Dllvm-mca.cpp380 unsigned Width = SM.IssueWidth; in main()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp312 if (Packet.size() >= InstrItins->SchedModel.IssueWidth) { in reserveResources()

123