Searched refs:IsVector (Results 1 – 6 of 6) sorted by relevance
78 explicit LLT() : IsPointer(false), IsVector(false), RawData(0) {} in LLT()88 bool isVector() const { return isValid() && IsVector; } in isVector()109 if (!IsVector) { in getScalarSizeInBits()125 if (!IsVector) in getAddressSpace()143 return IsPointer == RHS.IsPointer && IsVector == RHS.IsVector &&195 uint64_t IsVector : 1;213 void init(bool IsPointer, bool IsVector, uint16_t NumElements,216 this->IsVector = IsVector;217 if (!IsVector) {238 ((uint64_t)IsVector);[all …]
32 IsVector = false; in LLT()
177 bool IsVector = TII->isVector(MI); in runOnMachineFunction() local179 if (!IsReduction && !IsVector && !IsCube) { in runOnMachineFunction()
1447 bool IsVector) { in emitRegSave() argument1454 assert(Reg < (IsVector ? 32U : 16U) && "Register out of range"); in emitRegSave()1466 SPOffset -= Count * (IsVector ? 8 : 4); in emitRegSave()1470 if (IsVector) in emitRegSave()
411 bool parseDirectiveRegSave(SMLoc L, bool IsVector);10016 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) { in parseDirectiveRegSave() argument10031 if (!IsVector && !Op.isRegList()) in parseDirectiveRegSave()10033 if (IsVector && !Op.isDPRRegList()) in parseDirectiveRegSave()10036 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector); in parseDirectiveRegSave()
6573 bool IsVector = false; in EmitVAArg() local6583 IsVector = ArgTy->isVectorTy(); in EmitVAArg()6588 if (IsVector && UnpaddedSize > PaddedSize) in EmitVAArg()6598 if (IsVector) { in EmitVAArg()