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Searched refs:IsSub (Results 1 – 7 of 7) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DAggressiveAntiDepBreaker.cpp602 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters() local
606 if (!IsSub) in FindSuitableFreeRegisters()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonConstExtenders.cpp1781 bool IsSub = ExtOpc == Hexagon::S4_subaddi; in replaceInstrExpr() local
1782 Register Rs = MI.getOperand(IsSub ? 3 : 2); in replaceInstrExpr()
1783 ExtValue V = MI.getOperand(IsSub ? 2 : 3); in replaceInstrExpr()
1784 assert(EV == V && Rs == Ex.Rs && IsSub == Ex.Neg && "Initializer mismatch"); in replaceInstrExpr()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp383 bool IsSub = Offset < 0; in BuildStackAdjustment() local
384 uint64_t AbsOffset = IsSub ? -Offset : Offset; in BuildStackAdjustment()
385 unsigned Opc = IsSub ? getSUBriOpcode(Uses64BitFramePtr, AbsOffset) in BuildStackAdjustment()
H A DX86ISelLowering.cpp40404 bool IsSub = N->getOpcode() == ISD::SUB; in combineAddOrSubToADCOrSBB() local
40410 if (!IsSub && X.getOpcode() == ISD::ZERO_EXTEND && in combineAddOrSubToADCOrSBB()
40424 if (!IsSub && !PeekedThroughZext && X.getOpcode() == X86ISD::SETCC && in combineAddOrSubToADCOrSBB()
40440 (IsSub && CC == X86::COND_B && ConstantX->isNullValue())) { in combineAddOrSubToADCOrSBB()
40450 (IsSub && CC == X86::COND_A && ConstantX->isNullValue())) { in combineAddOrSubToADCOrSBB()
40472 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, in combineAddOrSubToADCOrSBB()
40492 return DAG.getNode(IsSub ? X86ISD::SBB : X86ISD::ADC, DL, in combineAddOrSubToADCOrSBB()
40517 if ((IsSub && CC == X86::COND_NE && ConstantX->isNullValue()) || in combineAddOrSubToADCOrSBB()
40531 if ((IsSub && CC == X86::COND_E && ConstantX->isNullValue()) || in combineAddOrSubToADCOrSBB()
40550 return DAG.getNode(IsSub ? X86ISD::ADC : X86ISD::SBB, DL, VTs, X, in combineAddOrSubToADCOrSBB()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2909 bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr || in optimizeCompareInstr() local
2911 if (!IsSub || (SrcReg2 != 0 && SubAdd->getOperand(1).getReg() == SrcReg2 && in optimizeCompareInstr()
2917 ARMCC::CondCodes NewCC = (IsSub ? getSwappedCondition(CC) : getCmpToAddCondition(CC)); in optimizeCompareInstr()
/freebsd-12.1/contrib/llvm/tools/clang/lib/AST/
H A DExprConstant.cpp8912 bool IsSub) { in addOrSubLValueAsInteger() argument
8920 Offset = CharUnits::fromQuantity(IsSub ? Offset64 - Index64 in addOrSubLValueAsInteger()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp13045 bool IsSub = (LD->getAddressingMode() == ISD::PRE_DEC || in ForwardStoreValueToDirectLoad() local
13047 unsigned Opc = IsSub ? ISD::SUB : ISD::ADD; in ForwardStoreValueToDirectLoad()