| /freebsd-12.1/contrib/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsNaClELFStreamer.cpp | 159 bool IsStore; in EmitInstruction() local
161 &IsStore); in EmitInstruction()
167 bool MaskAfter = IsSPFirstOperand && !IsStore; in EmitInstruction()
212 bool *IsStore) { in isBasePlusOffsetMemoryAccess() argument
213 if (IsStore) in isBasePlusOffsetMemoryAccess()
214 *IsStore = false; in isBasePlusOffsetMemoryAccess()
244 if (IsStore) in isBasePlusOffsetMemoryAccess()
245 *IsStore = true; in isBasePlusOffsetMemoryAccess()
252 if (IsStore) in isBasePlusOffsetMemoryAccess()
253 *IsStore = true; in isBasePlusOffsetMemoryAccess()
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| H A D | MipsMCNaCl.h | 21 bool *IsStore = nullptr);
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| /freebsd-12.1/contrib/llvm/lib/Transforms/Instrumentation/ |
| H A D | EfficiencySanitizer.cpp | 192 bool instrumentFastpath(Instruction *I, const DataLayout &DL, bool IsStore,
649 bool IsStore; in instrumentLoadOrStore() local
653 IsStore = false; in instrumentLoadOrStore()
657 IsStore = true; in instrumentLoadOrStore()
661 IsStore = true; in instrumentLoadOrStore()
665 IsStore = true; in instrumentLoadOrStore()
679 if (IsStore) in instrumentLoadOrStore()
685 OnAccessFunc = IsStore ? EsanUnalignedStoreN : EsanUnalignedLoadN; in instrumentLoadOrStore()
691 instrumentFastpath(I, DL, IsStore, Addr, Alignment)) { in instrumentLoadOrStore()
696 OnAccessFunc = IsStore ? EsanAlignedStore[Idx] : EsanAlignedLoad[Idx]; in instrumentLoadOrStore()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCVSXSwapRemoval.cpp | 80 unsigned int IsStore : 1; member
371 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
377 SwapVector[VecIdx].IsStore = 1; in gatherVectorInstructions()
684 SwapVector[UseIdx].IsStore) { in recordUnoptimizableWebs()
700 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
708 SwapVector[DefIdx].IsStore) { in recordUnoptimizableWebs()
774 } else if (SwapVector[EntryIdx].IsStore && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
986 if (SwapVector[EntryIdx].IsStore) in dumpSwapVector()
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| /freebsd-12.1/contrib/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXInstrFormats.td | 37 bit IsStore = 0;
53 let TSFlags{6-6} = IsStore;
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| /freebsd-12.1/contrib/llvm/include/llvm/Target/ |
| H A D | TargetSelectionDAG.td | 656 bit IsStore = ?;
940 let IsStore = 1;
945 let IsStore = 1;
952 let IsStore = 1;
957 let IsStore = 1;
962 let IsStore = 1;
967 let IsStore = 1;
972 let IsStore = 1;
977 let IsStore = 1;
983 let IsStore = 1;
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| /freebsd-12.1/contrib/llvm/utils/TableGen/ |
| H A D | X86FoldTablesEmitter.cpp | 101 bool IsStore = false; member in __anon7deb7ac00111::X86FoldTablesEmitter::X86FoldTableEntry
116 if (E.IsStore) in operator <<()
462 Result.IsStore = true; in addEntryWithFlags()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 467 bool IsStore = Entry.WideOpc == ARM::t2STR_POST; in ReduceLoadStore() local
468 unsigned Rt = MI->getOperand(IsStore ? 1 : 0).getReg(); in ReduceLoadStore()
469 unsigned Rn = MI->getOperand(IsStore ? 0 : 1).getReg(); in ReduceLoadStore()
486 .addReg(Rt, IsStore ? 0 : RegState::Define); in ReduceLoadStore()
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| H A D | ARMLoadStoreOptimizer.cpp | 497 bool IsStore = in UpdateBaseRegUses() local
500 if (IsLoad || IsStore) { in UpdateBaseRegUses()
513 if (Offset >= 0 && !(IsStore && InstrSrcReg == Base)) in UpdateBaseRegUses()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 492 bool IsStore = MI->mayStore(); in buildMUBUFOffsetLoadStore() local
495 int LoadStoreOp = IsStore ? in buildMUBUFOffsetLoadStore()
537 bool IsStore = Desc.mayStore(); in buildSpillLoadStore() local
593 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildSpillLoadStore()
606 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
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| /freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/ |
| H A D | CGAtomic.cpp | 1204 bool IsStore = E->getOp() == AtomicExpr::AO__c11_atomic_store || in EmitAtomicExpr() local
1225 if (IsStore) in EmitAtomicExpr()
1237 if (IsLoad || IsStore) in EmitAtomicExpr()
1263 if (!IsStore) in EmitAtomicExpr()
1267 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1284 if (!IsStore) { in EmitAtomicExpr()
1302 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 822 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
823 if (!IsLoad && !IsStore) in canMoveMemTo()
845 bool Conflict = (L && IsStore) || S; in canMoveMemTo()
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| H A D | HexagonConstExtenders.cpp | 1146 bool IsStore = MI.mayStore(); in recordExtender() local
1155 if (IsLoad || IsStore) { in recordExtender()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86MCInstLower.cpp | 352 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() local
353 unsigned AddrBase = IsStore; in SimplifyShortMoveForm()
354 unsigned RegOp = IsStore ? 0 : 5; in SimplifyShortMoveForm()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 10502 bool IsStore = false; in performNEONPostLDSTCombine() local
10517 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
10519 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
10521 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
10529 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
10531 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
10533 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
10547 NumVecs = 2; IsStore = true; IsLaneOp = true; break; in performNEONPostLDSTCombine()
10555 if (IsStore) in performNEONPostLDSTCombine()
10574 if (IsLaneOp || IsStore) in performNEONPostLDSTCombine()
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