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Searched refs:IsRV64 (Results 1 – 10 of 10) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoC.td310 let Predicates = [HasStdExtC, IsRV64] in
340 let Predicates = [HasStdExtC, IsRV64] in
365 Predicates = [HasStdExtC, IsRV64] in
458 let Predicates = [HasStdExtC, IsRV64] in
511 let Predicates = [HasStdExtC, IsRV64] in
563 } // Predicates = [HasStdExtC, IsRV64]
583 } // Predicates = [HasStdExtC, IsRV64]
600 } // Predicates = [HasStdExtC, IsRV64]
640 } // Predicates = [HasStdExtC, IsRV64]
675 } // Predicates = [HasStdExtC, IsRV64]
[all …]
H A DRISCVInstrInfoM.td30 let Predicates = [HasStdExtM, IsRV64] in {
36 } // Predicates = [HasStdExtM, IsRV64]
53 let Predicates = [HasStdExtM, IsRV64] in {
82 } // Predicates = [HasStdExtM, IsRV64]
H A DRISCV.td50 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
H A DRISCVInstrInfoD.td147 let Predicates = [HasStdExtD, IsRV64] in {
175 } // Predicates = [HasStdExtD, IsRV64]
215 // [u]int<->double conversion patterns must be gated on IsRV32 or IsRV64, so
H A DRISCVInstrInfo.td426 let Predicates = [IsRV64] in {
445 } // Predicates = [IsRV64]
509 let Predicates = [IsRV64] in {
512 } // Predicates = [IsRV64]
610 let Predicates = [IsRV64] in {
619 } // Predicates = [IsRV64]
916 let Predicates = [IsRV64] in {
972 } // Predicates = [IsRV64]
H A DRISCVInstrInfoF.td169 let Predicates = [HasStdExtF, IsRV64] in {
189 } // Predicates = [HasStdExtF, IsRV64]
255 // [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
H A DRISCVInstrInfoA.td76 let Predicates = [HasStdExtA, IsRV64] in {
88 } // Predicates = [HasStedExtA, IsRV64]
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/AsmParser/
H A DRISCVAsmParser.cpp172 bool IsRV64; member
203 IsRV64 = o.IsRV64; in RISCVOperand()
522 bool isRV64() const { return IsRV64; } in isRV64()
563 bool IsRV64) { in createToken()
568 Op->IsRV64 = IsRV64; in createToken()
573 SMLoc E, bool IsRV64) { in createReg()
578 Op->IsRV64 = IsRV64; in createReg()
583 SMLoc E, bool IsRV64) { in createImm()
588 Op->IsRV64 = IsRV64; in createImm()
593 createSysReg(StringRef Str, SMLoc S, unsigned Encoding, bool IsRV64) { in createSysReg()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/RISCV/Utils/
H A DRISCVMatInt.h33 void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
/freebsd-12.1/contrib/llvm/tools/clang/lib/Driver/ToolChains/
H A DGnu.cpp1469 bool IsRV64 = TargetTriple.getArch() == llvm::Triple::riscv64; in findRISCVMultilibs() local
1472 addMultilibFlag(!IsRV64, "m32", Flags); in findRISCVMultilibs()
1473 addMultilibFlag(IsRV64, "m64", Flags); in findRISCVMultilibs()