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Searched refs:IsLoad (Results 1 – 25 of 27) sorted by relevance

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/freebsd-12.1/contrib/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td654 bit IsLoad = ?;
797 let IsLoad = 1;
801 let IsLoad = 1;
807 let IsLoad = 1;
811 let IsLoad = 1;
815 let IsLoad = 1;
820 let IsLoad = 1;
824 let IsLoad = 1;
828 let IsLoad = 1;
832 let IsLoad = 1;
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCVSXSwapRemoval.cpp79 unsigned int IsLoad : 1; member
346 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
352 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
363 SwapVector[VecIdx].IsLoad = 1; in gatherVectorInstructions()
672 else if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in recordUnoptimizableWebs()
683 if (!SwapVector[UseIdx].IsSwap || SwapVector[UseIdx].IsLoad || in recordUnoptimizableWebs()
707 if (!SwapVector[DefIdx].IsSwap || SwapVector[DefIdx].IsLoad || in recordUnoptimizableWebs()
758 if (SwapVector[EntryIdx].IsLoad && SwapVector[EntryIdx].IsSwap) { in markSwapsForRemoval()
984 if (SwapVector[EntryIdx].IsLoad) in dumpSwapVector()
H A DPPCISelLowering.cpp7853 bool IsLoad = false; in haveEfficientBuildVectorPattern() local
7873 IsLoad = true; in haveEfficientBuildVectorPattern()
7877 (!IsLoad && !V->isOnlyUserOf(V->getOperand(i).getNode()))) in haveEfficientBuildVectorPattern()
7880 return !(IsSplat && IsLoad); in haveEfficientBuildVectorPattern()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXInstrFormats.td36 bit IsLoad = 0;
52 let TSFlags{5-5} = IsLoad;
/freebsd-12.1/contrib/llvm/include/llvm/Analysis/
H A DLoads.h127 bool *IsLoad, unsigned *NumScanedInst);
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DX86FoldTablesEmitter.cpp100 bool IsLoad = false; member in __anon7deb7ac00111::X86FoldTablesEmitter::X86FoldTableEntry
114 if (E.IsLoad) in operator <<()
460 Result.IsLoad = true; in addEntryWithFlags()
/freebsd-12.1/contrib/llvm/tools/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp308 bool IsLoad; member
317 : Checkers(checkers), Loc(loc), IsLoad(isLoad), NodeEx(NodeEx), in CheckLocationContext()
325 ProgramPoint::Kind K = IsLoad ? ProgramPoint::PreLoadKind : in runChecker()
332 checkFn(Loc, IsLoad, BoundEx, C); in runChecker()
/freebsd-12.1/contrib/llvm/lib/Analysis/
H A DLoads.cpp325 AliasAnalysis *AA, bool *IsLoad, in FindAvailableLoadedValue() argument
333 ScanFrom, MaxInstsToScan, AA, IsLoad, NumScanedInst); in FindAvailableLoadedValue()
/freebsd-12.1/contrib/llvm/lib/Target/X86/Utils/
H A DX86ShuffleDecode.h147 void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad,
H A DX86ShuffleDecode.cpp406 void DecodeScalarMoveMask(unsigned NumElts, bool IsLoad, in DecodeScalarMoveMask() argument
412 Mask.push_back(IsLoad ? static_cast<int>(SM_SentinelZero) : i); in DecodeScalarMoveMask()
/freebsd-12.1/contrib/llvm/tools/clang/lib/StaticAnalyzer/Checkers/
H A DCheckerDocumentation.cpp155 void checkLocation(SVal Loc, bool IsLoad, const Stmt *S, in checkLocation() argument
H A DObjCSuperDeallocChecker.cpp131 void ObjCSuperDeallocChecker::checkLocation(SVal L, bool IsLoad, const Stmt *S, in checkLocation() argument
H A DNSErrorChecker.cpp240 if (event.IsLoad) in checkEvent()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp495 bool IsLoad = in UpdateBaseRegUses() local
500 if (IsLoad || IsStore) { in UpdateBaseRegUses()
826 bool IsLoad = isi32Load(Opcode); in CreateLoadStoreDouble() local
827 assert((IsLoad || isi32Store(Opcode)) && "Must have integer load or store"); in CreateLoadStoreDouble()
828 unsigned LoadStoreOpcode = IsLoad ? ARM::t2LDRDi8 : ARM::t2STRDi8; in CreateLoadStoreDouble()
833 if (IsLoad) { in CreateLoadStoreDouble()
848 bool IsLoad = isLoadSingle(Opcode); in MergeOpsUpdate() local
863 if (IsLoad) { in MergeOpsUpdate()
H A DARMExpandPseudoInsts.cpp125 bool IsLoad; member
475 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); in ExpandVLD()
585 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); in ExpandVST()
683 if (TableEntry->IsLoad) { in ExpandLaneOp()
708 if (!TableEntry->IsLoad) in ExpandLaneOp()
733 if (TableEntry->IsLoad) in ExpandLaneOp()
H A DARMISelDAGToDAG.cpp200 void SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating,
2032 void ARMDAGToDAGISel::SelectVLDSTLane(SDNode *N, bool IsLoad, bool isUpdating, in SelectVLDSTLane() argument
2085 if (IsLoad) { in SelectVLDSTLane()
2137 if (!IsLoad) { in SelectVLDSTLane()
/freebsd-12.1/contrib/llvm/tools/clang/lib/CodeGen/
H A DCGAtomic.cpp1208 bool IsLoad = E->getOp() == AtomicExpr::AO__c11_atomic_load || in EmitAtomicExpr() local
1231 if (IsLoad) in EmitAtomicExpr()
1237 if (IsLoad || IsStore) in EmitAtomicExpr()
1265 if (!IsLoad) in EmitAtomicExpr()
1267 if (!IsLoad && !IsStore) in EmitAtomicExpr()
1294 if (!IsLoad) { in EmitAtomicExpr()
1302 if (!IsLoad && !IsStore) { in EmitAtomicExpr()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DInlineSpiller.cpp688 bool IsLoad = InstrReg; in coalesceStackAccess() local
689 if (!IsLoad) in coalesceStackAccess()
696 if (!IsLoad) in coalesceStackAccess()
703 if (IsLoad) { in coalesceStackAccess()
H A DMachineScheduler.cpp1526 bool IsLoad; member in __anon1997d06d0311::BaseMemOpClusterMutation
1530 const TargetRegisterInfo *tri, bool IsLoad) in BaseMemOpClusterMutation() argument
1531 : TII(tii), TRI(tri), IsLoad(IsLoad) {} in BaseMemOpClusterMutation()
1621 if ((IsLoad && !SU.getInstr()->mayLoad()) || in apply()
1622 (!IsLoad && !SU.getInstr()->mayStore())) in apply()
/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp1229 bool IsLoad = MI.getOpcode() == TargetOpcode::G_LOAD; in fewerElementsVector() local
1237 if (!IsLoad) in fewerElementsVector()
1252 if (IsLoad) { in fewerElementsVector()
1260 if (IsLoad) { in fewerElementsVector()
/freebsd-12.1/contrib/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp1274 bool IsLoad = fieldFromInstruction(insn, 22, 1); in DecodeSignedLdStInstruction() local
1279 if (IsLoad && IsIndexed && !IsFP && Rn != 31 && Rt == Rn) in DecodeSignedLdStInstruction()
1375 bool IsLoad = fieldFromInstruction(insn, 22, 1); in DecodePairLdStInstruction() local
1491 if (IsLoad && Rt == Rt2) in DecodePairLdStInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp822 bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); in canMoveMemTo() local
823 if (!IsLoad && !IsStore) in canMoveMemTo()
H A DHexagonConstExtenders.cpp1145 bool IsLoad = MI.mayLoad(); in recordExtender() local
1155 if (IsLoad || IsStore) { in recordExtender()
/freebsd-12.1/contrib/llvm/tools/clang/include/clang/StaticAnalyzer/Core/
H A DChecker.h554 bool IsLoad; member
/freebsd-12.1/contrib/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp247 const MCSubtargetInfo *STI, bool IsLoad);
302 const MCSubtargetInfo *STI, bool IsLoad);
3559 const MCSubtargetInfo *STI, bool IsLoad) { in expandMemInst() argument
3578 if (!IsLoad || !IsGPR || (BaseReg == DstReg)) { in expandMemInst()
3616 if (IsLoad) in expandMemInst()
4820 bool IsLoad) { in expandLoadStoreDMacro() argument
4827 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; in expandLoadStoreDMacro()
4848 if (FirstReg != BaseReg || !IsLoad) { in expandLoadStoreDMacro()

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