| /freebsd-12.1/contrib/llvm/lib/Object/ |
| H A D | Decompressor.cpp | 22 bool IsLE, bool Is64Bit) { in create() argument 28 : D.consumeCompressedZLibHeader(Is64Bit, IsLE); in create()
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| /freebsd-12.1/contrib/llvm/include/llvm/Object/ |
| H A D | Decompressor.h | 29 bool IsLE, bool Is64Bit);
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsMSAInstrInfo.td | 3599 def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>; 3600 def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>; 3601 def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>; 3602 def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>; 3603 def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>; 3604 def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>; 3606 def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>; 3607 def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>; 3608 def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>; 3609 def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>; [all …]
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| H A D | MipsInstrInfo.td | 231 def IsLE : Predicate<"Subtarget->isLittle()">;
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.h | 509 bool &Swap, bool IsLE); 530 bool &Swap, bool IsLE); 550 unsigned &InsertAtByte, bool &Swap, bool IsLE);
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| H A D | PPCISelLowering.cpp | 1422 if (IsLE) in isVPKUHUMShuffleMask() 1428 if (!IsLE) in isVPKUHUMShuffleMask() 1434 unsigned j = IsLE ? 0 : 1; in isVPKUHUMShuffleMask() 1453 if (IsLE) in isVPKUWUMShuffleMask() 1460 if (!IsLE) in isVPKUWUMShuffleMask() 1467 unsigned j = IsLE ? 0 : 2; in isVPKUWUMShuffleMask() 1495 if (IsLE) in isVPKUDUMShuffleMask() 1504 if (!IsLE) in isVPKUDUMShuffleMask() 1513 unsigned j = IsLE ? 0 : 4; in isVPKUDUMShuffleMask() 1914 if (IsLE) { in isXXSLDWIShuffleMask() [all …]
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| /freebsd-12.1/contrib/llvm/tools/lld/ELF/ |
| H A D | Config.h | 241 bool IsLE; member
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| H A D | Driver.cpp | 1010 Config->IsLE = (K == ELF32LEKind || K == ELF64LEKind); in setConfigs() 1011 Config->Endianness = Config->IsLE ? endianness::little : endianness::big; in setConfigs()
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| H A D | Writer.cpp | 2383 EHdr->e_ident[EI_DATA] = Config->IsLE ? ELFDATA2LSB : ELFDATA2MSB; in writeHeader()
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| H A D | SyntheticSections.cpp | 2459 DWARFDebugPubTable Table(Obj, *Pub, Config->IsLE, true); in readPubNamesAndTypes()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.td | 1834 let Predicates = [IsLE] in { 1847 let Predicates = [IsLE] in { 1974 let Predicates = [IsLE] in { 1993 let Predicates = [IsLE] in { 2159 let Predicates = [IsLE] in { 2177 let Predicates = [IsLE] in { 2493 let Predicates = [IsLE] in { 2585 let Predicates = [IsLE] in { 2609 let Predicates = [IsLE] in { 2722 let Predicates = [IsLE] in { [all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMInstrNEON.td | 7130 let Predicates = [IsLE] in { 7136 let Predicates = [IsLE] in { 7144 let Predicates = [IsLE] in { 7157 let Predicates = [IsLE] in { 7168 let Predicates = [IsLE] in { 7173 let Predicates = [IsLE] in { 7179 let Predicates = [IsLE] in { 7187 let Predicates = [IsLE] in { 7202 let Predicates = [IsLE] in { 7208 let Predicates = [IsLE] in { [all …]
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| H A D | ARMInstrThumb.td | 1581 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1583 Requires<[IsThumb, IsThumb1Only, IsLE]>; 1585 Requires<[IsThumb, IsThumb1Only, IsLE]>;
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| H A D | ARMInstrInfo.td | 391 def IsLE : Predicate<"MF->getDataLayout().isLittleEndian()">;
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| /freebsd-12.1/contrib/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCompares.cpp | 4575 bool IsLE = (Pred == ICmpInst::ICMP_SLE || Pred == ICmpInst::ICMP_ULE); in canonicalizeCmpWithConstant() local 4579 assert(IsLE ? !CI->isMaxValue(IsSigned) : !CI->isMinValue(IsSigned)); in canonicalizeCmpWithConstant() 4596 if (!CI || (IsLE ? CI->isMaxValue(IsSigned) : CI->isMinValue(IsSigned))) in canonicalizeCmpWithConstant() 4606 Constant *OneOrNegOne = ConstantInt::get(Op1Type, IsLE ? 1 : -1, true); in canonicalizeCmpWithConstant() 4607 CmpInst::Predicate NewPred = IsLE ? ICmpInst::ICMP_ULT: ICmpInst::ICMP_UGT; in canonicalizeCmpWithConstant()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | CodeGenPrepare.cpp | 6469 bool IsLE = SI.getModule()->getDataLayout().isLittleEndian(); in splitMergedValStore() local 6475 if ((IsLE && Upper) || (!IsLE && !Upper)) in splitMergedValStore()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAG.cpp | 2499 bool IsLE = getDataLayout().isLittleEndian(); in computeKnownBits() local 2518 unsigned Shifts = IsLE ? i : SubScale - 1 - i; in computeKnownBits() 2542 unsigned Shifts = IsLE ? i : NumElts - 1 - i; in computeKnownBits() 3379 bool IsLE = getDataLayout().isLittleEndian(); in ComputeNumSignBits() local 3401 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset); in ComputeNumSignBits()
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| H A D | DAGCombiner.cpp | 14280 bool IsLE = DAG.getDataLayout().isLittleEndian(); in MergeStoresOfConstantsOrVecElts() local 14282 unsigned Idx = IsLE ? (NumStores - 1 - i) : i; in MergeStoresOfConstantsOrVecElts() 15760 bool IsLE = DAG.getDataLayout().isLittleEndian(); in visitEXTRACT_VECTOR_ELT() local 15763 unsigned BCTruncElt = IsLE ? 0 : NumElts - 1; in visitEXTRACT_VECTOR_ELT() 15778 BCTruncElt = IsLE ? 0 : XBitWidth / VecEltBitWidth - 1; in visitEXTRACT_VECTOR_ELT()
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