| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | Mips16RegisterInfo.cpp | 126 bool IsKill = false; in eliminateFI() local
142 IsKill = true; in eliminateFI()
144 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| H A D | MipsSERegisterInfo.cpp | 201 bool IsKill = false; in eliminateFI() local
238 IsKill = true; in eliminateFI()
255 IsKill = true; in eliminateFI()
259 MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill); in eliminateFI()
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| H A D | MipsSEFrameLowering.cpp | 834 bool IsKill = !IsRAAndRetAddrIsTaken; in spillCalleeSavedRegisters() local
836 TII.storeRegToStackSlot(MBB, MI, Reg, IsKill, in spillCalleeSavedRegisters()
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| /freebsd-12.1/contrib/llvm/lib/Target/BPF/ |
| H A D | BPFInstrInfo.cpp | 127 unsigned SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
136 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
141 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 202 bool IsKill = false; in eliminateFrameIndex() local
228 IsKill = true; in eliminateFrameIndex()
231 MI.getOperand(FIOp).ChangeToRegister(BP, false, false, IsKill); in eliminateFrameIndex()
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| H A D | HexagonFrameLowering.cpp | 1269 bool IsKill = !HRI.isEHReturnCalleeSaveReg(Reg); in insertCSRSpillsInBlock() local
1273 if (IsKill) in insertCSRSpillsInBlock()
1600 bool IsKill = MI->getOperand(2).isKill(); in expandStoreInt() local
1609 .addReg(SrcR, getKillRegState(IsKill)); in expandStoreInt()
1663 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVecPred() local
1678 .addReg(SrcR, getKillRegState(IsKill)) in expandStoreVecPred()
1752 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec2() local
1767 .addReg(SrcLo, getKillRegState(IsKill)) in expandStoreVec2()
1778 .addReg(SrcHi, getKillRegState(IsKill)) in expandStoreVec2()
1839 bool IsKill = MI->getOperand(2).isKill(); in expandStoreVec() local
[all …]
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| H A D | HexagonBlockRanges.cpp | 327 bool IsKill = Op.isKill(); in computeInitialLiveRanges() local
330 if (IsKill) in computeInitialLiveRanges()
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| H A D | HexagonFrameLowering.h | 170 bool IsDef, bool IsKill) const;
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVInstrInfo.h | 41 bool IsKill, int FrameIndex,
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| H A D | RISCVInstrInfo.cpp | 111 unsigned SrcReg, bool IsKill, int FI, in storeRegToStackSlot() argument
131 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 523 bool IsKill, in buildSpillLoadStore() argument
597 SrcDstRegState |= getKillRegState(IsKill); in buildSpillLoadStore()
606 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill)) in buildSpillLoadStore()
663 bool IsKill = MI->getOperand(0).isKill(); in spillSGPR() local
703 unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill); in spillSGPR()
739 .addReg(SubReg, getKillRegState(IsKill)) // sdata in spillSGPR()
763 .addReg(SubReg, getKillRegState(IsKill)) in spillSGPR()
791 SuperKillState |= getKillRegState(IsKill); in spillSGPR()
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| H A D | SIInstrInfo.cpp | 1348 bool IsKill = RegOp.isKill(); in swapRegAndNonRegOperand() local
1360 NonRegOp.ChangeToRegister(Reg, false, false, IsKill, IsDead, IsUndef, IsDebug); in swapRegAndNonRegOperand()
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| /freebsd-12.1/contrib/llvm/lib/Target/AArch64/ |
| H A D | AArch64AdvSIMDScalarPass.cpp | 276 unsigned Dst, unsigned Src, bool IsKill) { in insertCopy() argument
279 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
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| H A D | AArch64InstrInfo.cpp | 2623 unsigned SrcReg, bool IsKill, in storeRegPairToStackSlot() argument
2635 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0) in storeRegPairToStackSlot()
2636 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1) in storeRegPairToStackSlot()
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| /freebsd-12.1/contrib/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.h | 58 unsigned SourceRegister, bool IsKill, int FrameIndex,
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| H A D | LanaiInstrInfo.cpp | 52 unsigned SourceRegister, bool IsKill, int FrameIndex, in storeRegToStackSlot() argument
64 .addReg(SourceRegister, getKillRegState(IsKill)) in storeRegToStackSlot()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | ScheduleDAGInstrs.cpp | 390 bool IsKill = MO.getSubReg() == 0 || MO.isUndef(); in addVRegDefDeps() local
394 KillLaneMask = IsKill ? LaneBitmask::getAll() : DefLaneMask; in addVRegDefDeps()
1053 bool IsKill = LiveRegs.available(MRI, Reg); in toggleKills() local
1054 MO.setIsKill(IsKill); in toggleKills()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/ |
| H A D | ARMLoadStoreOptimizer.cpp | 857 bool IsKill = MO.isKill(); in MergeOpsUpdate() local
858 if (IsKill) in MergeOpsUpdate()
860 Regs.push_back(std::make_pair(Reg, IsKill)); in MergeOpsUpdate()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 832 bool IsKill = MI.getOperand(1).isKill(); in convertToThreeAddressWithLEA() local
839 .addReg(Src, getKillRegState(IsKill)); in convertToThreeAddressWithLEA()
905 if (IsKill) in convertToThreeAddressWithLEA()
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