| /freebsd-12.1/contrib/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 867 static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT, in getVectorTypeBreakdownMVT() argument
896 IntermediateVT = NewVT; in getVectorTypeBreakdownMVT()
1220 MVT IntermediateVT; in computeRegisterProperties() local
1223 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT, in computeRegisterProperties()
1283 EVT &IntermediateVT, in getVectorTypeBreakdown() argument
1297 IntermediateVT = RegisterEVT; in getVectorTypeBreakdown()
1329 IntermediateVT = NewVT; in getVectorTypeBreakdown()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.h | 37 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | SIISelLowering.cpp | 782 EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
790 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
797 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
807 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
814 Context, CC, VT, IntermediateVT, NumIntermediates, RegisterVT); in getVectorTypeBreakdownForCallingConv()
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| /freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | SelectionDAGBuilder.cpp | 360 EVT IntermediateVT; in getCopyFromPartsVector() local
389 PartVT, IntermediateVT, V); in getCopyFromPartsVector()
398 PartVT, IntermediateVT, V); in getCopyFromPartsVector()
405 (IntermediateVT.isVector() in getCopyFromPartsVector()
408 Val = DAG.getNode(IntermediateVT.isVector() ? ISD::CONCAT_VECTORS in getCopyFromPartsVector()
693 EVT IntermediateVT; in getCopyToPartsVector() local
699 *DAG.getContext(), CallConv.getValue(), ValueVT, IntermediateVT, in getCopyToPartsVector()
711 unsigned IntermediateNumElts = IntermediateVT.isVector() ? in getCopyToPartsVector()
712 IntermediateVT.getVectorNumElements() : 1; in getCopyToPartsVector()
730 if (IntermediateVT.isVector()) { in getCopyToPartsVector()
[all …]
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| /freebsd-12.1/contrib/llvm/include/llvm/CodeGen/ |
| H A D | TargetLowering.h | 728 EVT &IntermediateVT,
736 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
738 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates, in getVectorTypeBreakdownForCallingConv()
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsISelLowering.h | 302 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT,
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| H A D | MipsISelLowering.cpp | 139 LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, in getVectorTypeBreakdownForCallingConv() argument
143 IntermediateVT = RegisterVT; in getVectorTypeBreakdownForCallingConv()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 7321 MVT IntermediateVT = FourEltRes ? MVT::v4i32 : MVT::v2i64; in LowerINT_TO_FPVector() local
7344 Arrange = DAG.getBitcast(IntermediateVT, Arrange); in LowerINT_TO_FPVector()
7345 Extend = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, IntermediateVT, Arrange, in LowerINT_TO_FPVector()
7348 Extend = DAG.getNode(ExtendOp, dl, IntermediateVT, Arrange); in LowerINT_TO_FPVector()
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