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Searched refs:IntRegs (Results 1 – 19 of 19) sorted by relevance

/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonDepMapAsm2Intrin.td47 def: Pat<(int_hexagon_M2_mpy_nac_sat_hl_s1 IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
127 def: Pat<(int_hexagon_S2_asr_r_r_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
133 def: Pat<(int_hexagon_M2_subacc IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
187 def: Pat<(int_hexagon_F2_sffma IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
195 def: Pat<(int_hexagon_F2_sffma_lib IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
259 def: Pat<(int_hexagon_M4_and_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
383 def: Pat<(int_hexagon_M4_or_and IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
441 def: Pat<(int_hexagon_M4_or_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
459 def: Pat<(int_hexagon_M4_and_xor IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
589 def: Pat<(int_hexagon_M4_or_or IntRegs:$src1, IntRegs:$src2, IntRegs:$src3),
[all …]
H A DHexagonIntrinsics.td24 def: Pat<(int_hexagon_A2_add IntRegs:$Rs, IntRegs:$Rt),
25 (A2_add IntRegs:$Rs, IntRegs:$Rt)>;
31 def: Pat<(int_hexagon_A2_sub IntRegs:$Rs, IntRegs:$Rt),
32 (A2_sub IntRegs:$Rs, IntRegs:$Rt)>;
39 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
41 (M2_mpyi IntRegs:$Rs, IntRegs:$Rt)>;
45 (M2_dpmpyss_s0 IntRegs:$Rs, IntRegs:$Rt)>;
47 (M2_dpmpyuu_s0 IntRegs:$Rs, IntRegs:$Rt)>;
63 (A2_and IntRegs:$Rs, IntRegs:$Rt)>;
67 (A2_or IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
H A DHexagonDepMappings.td12 def A2_negAlias : InstAlias<"$Rd32 = neg($Rs32)", (A2_subri IntRegs:$Rd32, 0, IntRegs:$Rs32)>;
13 def A2_notAlias : InstAlias<"$Rd32 = not($Rs32)", (A2_subri IntRegs:$Rd32, -1, IntRegs:$Rs32)>;
14 …fAlias : InstAlias<"if (!$Pu4) $Rd32 = $Rs32", (A2_paddif IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
16 …rtAlias : InstAlias<"if ($Pu4) $Rd32 = $Rs32", (A2_paddit IntRegs:$Rd32, PredRegs:$Pu4, IntRegs:$R…
20 def A2_zxtbAlias : InstAlias<"$Rd32 = zxtb($Rs32)", (A2_andir IntRegs:$Rd32, IntRegs:$Rs32, 255)>;
35 def L2_loadrb_zomapAlias : InstAlias<"$Rd32 = memb($Rs32)", (L2_loadrb_io IntRegs:$Rd32, IntRegs:$R…
37 def L2_loadrh_zomapAlias : InstAlias<"$Rd32 = memh($Rs32)", (L2_loadrh_io IntRegs:$Rd32, IntRegs:$R…
38 def L2_loadri_zomapAlias : InstAlias<"$Rd32 = memw($Rs32)", (L2_loadri_io IntRegs:$Rd32, IntRegs:$R…
39 def L2_loadrub_zomapAlias : InstAlias<"$Rd32 = memub($Rs32)", (L2_loadrub_io IntRegs:$Rd32, IntRegs…
40 def L2_loadruh_zomapAlias : InstAlias<"$Rd32 = memuh($Rs32)", (L2_loadruh_io IntRegs:$Rd32, IntRegs…
[all …]
H A DHexagonMapAsm2IntrinV65.gen.td21 …xagon_V6_vaslh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src…
22 …_V6_vaslh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vaslh_acc HvxVR:$src1, HvxVR:$src…
23 …xagon_V6_vasrh_acc HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src…
24 …_V6_vasrh_acc_128B HvxVR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vasrh_acc HvxVR:$src1, HvxVR:$src…
37 def: Pat<(int_hexagon_V6_vmpabuu HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs:$src…
38 def: Pat<(int_hexagon_V6_vmpabuu_128B HvxWR:$src1, IntRegs:$src2), (V6_vmpabuu HvxWR:$src1, IntRegs…
39 …on_V6_vmpabuu_acc HvxWR:$src1, HvxWR:$src2, IntRegs:$src3), (V6_vmpabuu_acc HvxWR:$src1, HvxWR:$sr…
47 …xagon_V6_vmpyh_acc HvxWR:$src1, HvxVR:$src2, IntRegs:$src3), (V6_vmpyh_acc HvxWR:$src1, HvxVR:$src…
49 def: Pat<(int_hexagon_V6_vmpyuhe HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs:$src…
50 def: Pat<(int_hexagon_V6_vmpyuhe_128B HvxVR:$src1, IntRegs:$src2), (V6_vmpyuhe HvxVR:$src1, IntRegs…
[all …]
H A DHexagonDepInstrInfo.td46 (ins IntRegs:$Rs32, IntRegs:$Rt32),
62 (ins IntRegs:$Rt32, IntRegs:$Rs32),
74 (ins IntRegs:$Rt32, IntRegs:$Rs32),
86 (ins IntRegs:$Rt32, IntRegs:$Rs32),
98 (ins IntRegs:$Rt32, IntRegs:$Rs32),
110 (ins IntRegs:$Rt32, IntRegs:$Rs32),
4567 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4581 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4609 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
4623 (ins IntRegs:$Rx32in, IntRegs:$Rs32, IntRegs:$Rt32),
[all …]
H A DHexagonMapAsm2IntrinV62.gen.td11 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
12 (MI HvxVR:$src1, IntRegs:$src2)>;
14 (MI HvxVR:$src1, IntRegs:$src2)>;
48 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
49 (MI HvxWR:$src1, IntRegs:$src2)>;
51 (MI HvxWR:$src1, IntRegs:$src2)>;
72 (MI HvxQR:$src1, IntRegs:$src2)>;
74 (MI HvxQR:$src1, IntRegs:$src2)>;
93 def: Pat<(IntID IntRegs:$src1),
94 (MI IntRegs:$src1)>;
[all …]
H A DHexagonIntrinsicsV60.td67 (V6_vS32b_ai IntRegs:$addr, 0,
71 def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
76 (V6_vS32b_ai IntRegs:$addr, 0,
86 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>;
88 (MI IntRegs:$src1)>;
116 def: Pat<(IntID HvxWR:$src1, IntRegs:$src2),
120 (MI HvxWR:$src1, IntRegs:$src2)>;
124 def: Pat<(IntID HvxVR:$src1, IntRegs:$src2),
128 (MI HvxVR:$src1, IntRegs:$src2)>;
156 def: Pat<(IntID HvxQR:$src1, IntRegs:$src2),
[all …]
H A DHexagonPatternsV65.td13 (ins IntRegs:$_dst_, IntRegs:$Rt,
22 (ins IntRegs:$_dst_, IntRegs:$Rt,
31 (ins IntRegs:$_dst_, IntRegs:$Rt,
44 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
53 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
62 (ins IntRegs:$_dst_, RC2:$Vq, IntRegs:$Rt,
H A DHexagonPseudo.td14 def I32 : PatLeaf<(i32 IntRegs:$R)>;
16 def F32 : PatLeaf<(f32 IntRegs:$R)>;
26 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
45 : InstHexagon<(outs IntRegs:$dst),
261 def PS_fi : Pseudo<(outs IntRegs:$Rd),
264 def PS_fia : Pseudo<(outs IntRegs:$Rd),
265 (ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
528 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, IntRegs:$Cs),
532 (ins IntRegs:$Rx32in, ModRegs:$Mu2, IntRegs:$Cs),
549 (ins IntRegs:$Rx32in, s4_0Imm:$Ii, ModRegs:$Mu2, RC:$Rt32, IntRegs:$Cs),
[all …]
H A DHexagonPatterns.td674 (A4_cmpbeq IntRegs:$Rs, IntRegs:$Rt)>;
678 (A4_cmpheq IntRegs:$Rs, IntRegs:$Rt)>;
849 (InstA IntRegs:$Rs, IntRegs:$Rt)>;
852 (InstB IntRegs:$Rs, IntRegs:$Rt)>;
1596 (M4_mpyrr_addr IntRegs:$Ru, IntRegs:$Ry, IntRegs:$Rs)>;
1679 (S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1681 (S2_setbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1714 (S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
1725 (C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
1730 (C2_bitsset IntRegs:$Rs, IntRegs:$Rt)>;
[all …]
H A DHexagonIntrinsicsV5.td178 def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
180 (S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
185 IntRegs:$src3, u2_0ImmPred:$src4),
187 IntRegs:$src3, u2_0ImmPred:$src4)>;
H A DHexagonRegisterInfo.td337 def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32,
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcInstrAliases.td23 (movrr IntRegs:$rd, IntRegs:$rs2, condVal)>;
48 (movrr IntRegs:$rd, FCCRegs:$cc, IntRegs:$rs2, condVal)>;
145 (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
155 (TXCCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
166 // (TICCrr IntRegs:$rs1, IntRegs:$rs2, condVal)>,
200 (TRAPrr IntRegs:$rs1, IntRegs:$rs2, condVal)>;
387 def : InstAlias<"inc $rd", (ADDri IntRegs:$rd, IntRegs:$rd, 1), 0>;
399 def : InstAlias<"dec $rd", (SUBri IntRegs:$rd, IntRegs:$rd, 1), 0>;
415 def : InstAlias<"bset $rs2, $rd", (ORrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
419 def : InstAlias<"bclr $rs2, $rd", (ANDNrr IntRegs:$rd, IntRegs:$rd, IntRegs:$rs2), 0>;
[all …]
H A DSparcInstrInfo.td328 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
453 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
475 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
653 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
663 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
672 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
1053 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
1524 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1535 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1546 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
[all …]
H A DSparcInstr64Bit.td23 def : Pat<(i32 (trunc i64:$val)), (COPY_TO_REGCLASS $val, IntRegs)>;
197 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
208 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
217 (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
244 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
317 def MOVXCCrr : F4_1<0b101100, (outs IntRegs:$rd),
318 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
322 def MOVXCCri : F4_2<0b101100, (outs IntRegs:$rd),
323 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
385 (ins I64Regs:$rs1, IntRegs:$rs2),
[all …]
H A DSparcRegisterInfo.td328 def IntRegs : RegisterClass<"SP", [i32, i64], 32,
334 // Should be in the same order as IntRegs.
343 // to be a sub-class of IntRegs. That works out because requiring a 64-bit
345 def I64Regs : RegisterClass<"SP", [i64], 64, (add IntRegs)>;
H A DSparcInstrFormats.td230 def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp128 static const MCPhysReg IntRegs[32] = { variable
1092 RegNo = IntRegs[intVal]; in matchRegisterName()
1100 RegNo = IntRegs[8 + intVal]; in matchRegisterName()
1107 RegNo = IntRegs[16 + intVal]; in matchRegisterName()
1114 RegNo = IntRegs[24 + intVal]; in matchRegisterName()
1138 RegNo = IntRegs[intVal]; in matchRegisterName()
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp2663 static const MCPhysReg IntRegs[] = { Mips::A0, Mips::A1, Mips::A2, Mips::A3 }; in CC_MipsO32() local
2725 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2728 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2732 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2737 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2739 Reg = State.AllocateReg(IntRegs); in CC_MipsO32()
2740 State.AllocateReg(IntRegs); in CC_MipsO32()
2747 State.AllocateReg(IntRegs); in CC_MipsO32()
2751 unsigned Reg2 = State.AllocateReg(IntRegs); in CC_MipsO32()
2753 State.AllocateReg(IntRegs); in CC_MipsO32()
[all …]