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Searched refs:InstrStage (Results 1 – 25 of 37) sorted by relevance

12

/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCSchedule440.td150 InstrStage<1, [P440_IWB]>],
158 InstrStage<1, [P440_IWB]>],
166 InstrStage<1, [P440_IWB]>],
173 InstrStage<1, [P440_IWB]>],
237 InstrStage<1, [P440_CRD]>,
244 InstrStage<1, [P440_CRD]>,
251 InstrStage<1, [P440_CRD]>,
258 InstrStage<1, [P440_CRD]>,
265 InstrStage<1, [P440_CRD]>,
272 InstrStage<1, [P440_CRD]>,
[all …]
H A DPPCScheduleP7.td92 InstrItinData<IIC_IntISEL, [InstrStage<1, [P7_DU1], 0>,
94 InstrStage<1, [P7_BRU]>],
101 InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>,
102 InstrStage<1, [P7_DU2], 0>,
105 InstrItinData<IIC_IntDivD , [InstrStage<1, [P7_DU1], 0>,
106 InstrStage<1, [P7_DU2], 0>,
150 InstrStage<1, [P7_BRU]>],
153 InstrStage<1, [P7_CRU]>],
156 InstrStage<1, [P7_BRU]>],
159 InstrStage<1, [P7_BRU]>],
[all …]
H A DPPCScheduleP8.td69 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>,
71 InstrStage<1, [P8_BRU]>],
126 InstrStage<1, [P8_BRU]>],
132 InstrItinData<IIC_BrCR , [InstrStage<1, [P8_DU1], 0>,
133 InstrStage<1, [P8_CRU]>],
138 InstrStage<1, [P8_CRU]>],
142 InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
145 InstrItinData<IIC_BrMCRX , [InstrStage<1, [P8_DU1], 0>,
153 InstrItinData<IIC_LdStLoadUpd , [InstrStage<1, [P8_DU1], 0>,
322 InstrStage<1, [P8_CRU]>],
[all …]
H A DPPCScheduleE5500.td73 InstrStage<1, [E5500_CFX_0], 0>,
85 InstrStage<1, [E5500_FPU_0]>],
89 InstrStage<7, [E5500_FPU_0]>],
94 InstrStage<2, [E5500_CFX_1]>],
100 InstrStage<1, [E5500_CFX_1]>],
106 InstrStage<1, [E5500_CFX_1]>],
112 InstrStage<2, [E5500_CFX_1]>],
137 InstrStage<2, [E5500_SFX0]>],
141 InstrStage<1, [E5500_BU]>],
145 InstrStage<1, [E5500_BU]>],
[all …]
H A DPPCScheduleG5.td32 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>,
33 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>,
34 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>,
35 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>,
41 InstrItinData<IIC_IntRFID , [InstrStage<1, [G5_IU2]>]>,
48 InstrItinData<IIC_BrB , [InstrStage<1, [G5_BPU]>]>,
49 InstrItinData<IIC_BrCR , [InstrStage<4, [G5_BPU]>]>,
50 InstrItinData<IIC_BrMCR , [InstrStage<2, [G5_BPU]>]>,
51 InstrItinData<IIC_BrMCRX , [InstrStage<3, [G5_BPU]>]>,
52 InstrItinData<IIC_LdStDCBF , [InstrStage<3, [G5_SLU]>]>,
[all …]
H A DPPCScheduleE500mc.td75 InstrStage<8, [E500mc_FPU_0]>],
79 InstrStage<8, [E500mc_FPU_0]>],
83 InstrStage<1, [E500mc_CFX_0]>],
88 InstrStage<1, [E500mc_CFX_0]>],
93 InstrStage<1, [E500mc_CFX_0]>],
108 InstrStage<2, [E500mc_SFX0]>],
112 InstrStage<1, [E500mc_BU]>],
116 InstrStage<1, [E500mc_BU]>],
121 InstrStage<1, [E500mc_BU]>],
129 InstrStage<1, [E500mc_LSU_0]>],
[all …]
H A DPPCScheduleG4.td31 InstrItinData<IIC_IntDivW , [InstrStage<19, [G4_IU1]>]>,
32 InstrItinData<IIC_IntMFFS , [InstrStage<3, [G4_FPU1]>]>,
33 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G4_VIU1]>]>,
34 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G4_FPU1]>]>,
35 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G4_IU1]>]>,
36 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G4_IU1]>]>,
37 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4_IU1]>]>,
41 InstrItinData<IIC_BrB , [InstrStage<1, [G4_BPU]>]>,
42 InstrItinData<IIC_BrCR , [InstrStage<1, [G4_SRU]>]>,
43 InstrItinData<IIC_BrMCR , [InstrStage<1, [G4_SRU]>]>,
[all …]
H A DPPCScheduleE500.td64 InstrStage<1, [E500_MU], 0>,
65 InstrStage<14, [E500_MU]>],
70 InstrStage<4, [E500_MU]>],
75 InstrStage<4, [E500_MU]>],
80 InstrStage<4, [E500_MU]>],
95 InstrStage<2, [E500_SU0]>],
99 InstrStage<1, [E500_BU]>],
103 InstrStage<1, [E500_BU]>],
108 InstrStage<1, [E500_BU]>],
243 InstrStage<6, [E500_MU]>],
[all …]
H A DPPCScheduleG4Plus.td36 InstrItinData<IIC_IntDivW , [InstrStage<23, [G4P_IU2]>]>,
37 InstrItinData<IIC_IntMFFS , [InstrStage<5, [G4P_FPU1]>]>,
38 InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [G4P_VFPU]>]>,
39 InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [G4P_FPU1]>]>,
40 InstrItinData<IIC_IntMulHW , [InstrStage<4, [G4P_IU2]>]>,
41 InstrItinData<IIC_IntMulHWU , [InstrStage<4, [G4P_IU2]>]>,
42 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G4P_IU2]>]>,
49 InstrItinData<IIC_BrB , [InstrStage<1, [G4P_BPU]>]>,
50 InstrItinData<IIC_BrCR , [InstrStage<2, [G4P_IU2]>]>,
51 InstrItinData<IIC_BrMCR , [InstrStage<2, [G4P_IU2]>]>,
[all …]
H A DPPCScheduleG3.td26 InstrItinData<IIC_IntDivW , [InstrStage<19, [G3_IU1]>]>,
27 InstrItinData<IIC_IntMFFS , [InstrStage<1, [G3_FPU1]>]>,
28 InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [G3_FPU1]>]>,
29 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G3_IU1]>]>,
30 InstrItinData<IIC_IntMulHWU , [InstrStage<6, [G3_IU1]>]>,
31 InstrItinData<IIC_IntMulLI , [InstrStage<3, [G3_IU1]>]>,
35 InstrItinData<IIC_BrB , [InstrStage<1, [G3_BPU]>]>,
36 InstrItinData<IIC_BrCR , [InstrStage<1, [G3_SRU]>]>,
37 InstrItinData<IIC_BrMCR , [InstrStage<1, [G3_SRU]>]>,
38 InstrItinData<IIC_BrMCRX , [InstrStage<1, [G3_SRU]>]>,
[all …]
H A DPPCScheduleA2.td28 InstrItinData<IIC_IntSimple, [InstrStage<1, [A2_XU]>],
30 InstrItinData<IIC_IntGeneral, [InstrStage<1, [A2_XU]>],
32 InstrItinData<IIC_IntISEL, [InstrStage<1, [A2_XU]>],
34 InstrItinData<IIC_IntCompare, [InstrStage<1, [A2_XU]>],
36 InstrItinData<IIC_IntDivW, [InstrStage<1, [A2_XU]>],
38 InstrItinData<IIC_IntDivD, [InstrStage<1, [A2_XU]>],
40 InstrItinData<IIC_IntMulHW, [InstrStage<1, [A2_XU]>],
42 InstrItinData<IIC_IntMulHWU, [InstrStage<1, [A2_XU]>],
44 InstrItinData<IIC_IntMulLI, [InstrStage<1, [A2_XU]>],
46 InstrItinData<IIC_IntRotate, [InstrStage<1, [A2_XU]>],
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMScheduleA8.td154 InstrStage<2, [A8_LSPipe]>],
164 InstrStage<3, [A8_LSPipe]>,
175 InstrStage<3, [A8_LSPipe]>,
181 InstrStage<1, [A8_LSPipe]>,
362 InstrStage<1, [A8_NPipe]>],
367 InstrStage<1, [A8_NPipe]>],
372 InstrStage<1, [A8_NPipe]>],
377 InstrStage<1, [A8_NPipe]>],
397 InstrStage<1, [A8_LSPipe]>,
405 InstrStage<1, [A8_LSPipe]>,
[all …]
H A DARMScheduleA9.td64 InstrStage<1, [A9_MUX0], 0>,
65 InstrStage<1, [A9_AGU], 0>,
177 InstrStage<2, [A9_ALU0]>],
182 InstrStage<2, [A9_ALU0]>],
187 InstrStage<3, [A9_ALU0]>],
459 InstrStage<1, [A9_MUX0], 0>,
462 InstrStage<1, [A9_NPipe]>],
471 InstrStage<1, [A9_NPipe]>],
480 InstrStage<1, [A9_NPipe]>],
490 InstrStage<1, [A9_NPipe]>],
[all …]
H A DARMScheduleV6.td25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>,
65 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [V6_Pipe]>,
67 InstrItinData<IIC_iMOVix2addpc,[InstrStage<1, [V6_Pipe]>,
68 InstrStage<1, [V6_Pipe]>,
70 InstrItinData<IIC_iMOVix2ld , [InstrStage<1, [V6_Pipe]>,
71 InstrStage<1, [V6_Pipe]>,
79 InstrItinData<IIC_iCMOVix2 , [InstrStage<1, [V6_Pipe]>,
134 InstrItinData<IIC_iLoad_mBr, [InstrStage<3, [V6_Pipe]>,
139 InstrItinData<IIC_iLoadiALU, [InstrStage<1, [V6_Pipe]>,
147 InstrItinData<IIC_iPop_Br, [InstrStage<3, [V6_Pipe]>,
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonDepIICHVX.td112 [InstrStage<1, [SLOT1], 0>,
113 InstrStage<1, [CVI_LD], 0>,
118 [InstrStage<1, [SLOT1], 0>,
119 InstrStage<1, [CVI_LD], 0>,
144 [InstrStage<1, [SLOT0], 0>,
145 InstrStage<1, [SLOT1], 0>,
167 [InstrStage<1, [SLOT0], 0>,
184 [InstrStage<1, [SLOT0], 0>,
234 [InstrStage<1, [SLOT0], 0>,
235 InstrStage<1, [SLOT1], 0>,
[all …]
H A DHexagonDepIICScalar.td418 [InstrStage<1, [SLOT3]>], [1],
498 [InstrStage<1, [SLOT0]>], [],
526 [InstrStage<1, [SLOT2]>], [1],
562 [InstrStage<1, [SLOT0]>], [2],
718 [InstrStage<1, [SLOT2]>], [],
730 [InstrStage<1, [SLOT0]>], [],
750 [InstrStage<1, [SLOT3]>], [],
826 [InstrStage<1, [SLOT0]>], [],
1186 [InstrStage<1, [SLOT0]>], [],
1406 [InstrStage<1, [SLOT2]>], [],
[all …]
H A DHexagonIICScalar.td16 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
18 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
19 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
20 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
21 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
27 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
29 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
H A DHexagonScheduleV5.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
16 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
17 InstrStage<1, [SLOT2, SLOT3]>]>,
18 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>,
19 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>
25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
H A DHexagonScheduleV55.td13 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
17 InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
18 InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
25 InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
26 InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
H A DHexagonIICHVX.td16 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
17 InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
25 [InstrStage<1, [SLOT0], 0>,
26 InstrStage<1, [CVI_LD], 0>, InstrStage<1, [CVI_ST], 0>,
27 InstrStage<1, [CVI_MPY01, CVI_XLSHF]>]>];
/freebsd-12.1/contrib/llvm/lib/Target/Mips/
H A DMipsSchedule.td385 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>,
386 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>,
387 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>,
388 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>,
389 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>,
390 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>,
391 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>,
392 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>,
393 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>,
394 InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>,
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/Sparc/
H A DSparcSchedule.td46 InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
53 InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [5, 1]>,
54 InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [5, 1]>,
55 InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
64 InstrItinData<IIC_fpu_abs, [InstrStage<1, [LEONFPU]>], [2, 1]>,
67 InstrItinData<IIC_fpu_stod, [InstrStage<1, [LEONFPU]>], [2, 1]>
73 InstrItinData<IIC_iu_instr, [InstrStage<1, [LEONIU]>], [1, 1]>,
80 InstrItinData<IIC_iu_smul, [InstrStage<1, [LEONIU]>], [1, 1]>,
81 InstrItinData<IIC_iu_umul, [InstrStage<1, [LEONIU]>], [4, 1]>,
82 InstrItinData<IIC_iu_div, [InstrStage<1, [LEONIU]>], [35, 1]>,
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600Schedule.td32 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
33 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
34 InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
35 InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>,
36 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
44 InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
45 InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
46 InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
47 InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp46 const InstrStage *IS = ItinData->beginStage(idx); in ScoreboardHazardRecognizer()
47 const InstrStage *E = ItinData->endStage(idx); in ScoreboardHazardRecognizer()
129 for (const InstrStage *IS = ItinData->beginStage(idx), in getHazardType()
148 case InstrStage::Required: in getHazardType()
152 case InstrStage::Reserved: in getHazardType()
188 for (const InstrStage *IS = ItinData->beginStage(idx), in EmitInstruction()
199 case InstrStage::Required: in EmitInstruction()
203 case InstrStage::Reserved: in EmitInstruction()
216 if (IS->getReservationKind() == InstrStage::Required) in EmitInstruction()
/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrItineraries.h59 struct InstrStage { struct
111 const InstrStage *Stages = nullptr; ///< Array of stages selected
118 InstrItineraryData(const MCSchedModel &SM, const InstrStage *S, in InstrItineraryData()
133 const InstrStage *beginStage(unsigned ItinClassIndx) const { in beginStage()
139 const InstrStage *endStage(unsigned ItinClassIndx) const { in endStage()
155 for (const InstrStage *IS = beginStage(ItinClassIndx), in getStageLatency()

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