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Searched refs:Instr (Results 1 – 25 of 84) sorted by relevance

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/freebsd-12.1/contrib/llvm/tools/lld/ELF/
H A DAArch64ErrataFix.cpp121 return (Instr & 0xbfff0000) == 0x0d000000 && isST1SingleOpcode(Instr); in isST1Single()
126 return (Instr & 0xbfe00000) == 0x0d800000 && isST1SingleOpcode(Instr); in isST1SinglePost()
130 return isST1Multiple(Instr) || isST1MultiplePost(Instr) || in isST1()
131 isST1Single(Instr) || isST1SinglePost(Instr); in isST1()
183 return isSTPPost(Instr) || isSTPOffset(Instr) || isSTPPre(Instr); in isSTP()
224 static uint32_t getRt(uint32_t Instr) { return (Instr & 0x1f); } in getRt() argument
227 static uint32_t getRn(uint32_t Instr) { return (Instr >> 5) & 0x1f; } in getRn() argument
245 isLoadStoreUnpriv(Instr) || isLoadStoreImmediatePre(Instr) || in isV8SingleRegisterNonStructureLoadStore()
281 isSTPPre(Instr) || isSTPPost(Instr) || isST1SinglePost(Instr) || in hasWriteback()
289 return (isV8NonStructureLoad(Instr) && getRt(Instr) == Reg) || in doesLoadStoreWriteToReg()
[all …]
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMFeatures.h22 bool IsCPSRDead(const InstrType *Instr);
25 inline bool isV8EligibleForIT(const InstrType *Instr) { in isV8EligibleForIT() argument
26 switch (Instr->getOpcode()) { in isV8EligibleForIT()
53 return IsCPSRDead(Instr); in isV8EligibleForIT()
79 return Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
84 return Instr->getOperand(0).getReg() != ARM::PC; in isV8EligibleForIT()
86 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
87 Instr->getOperand(2).getReg() != ARM::PC; in isV8EligibleForIT()
90 return Instr->getOperand(0).getReg() != ARM::PC && in isV8EligibleForIT()
91 Instr->getOperand(1).getReg() != ARM::PC; in isV8EligibleForIT()
/freebsd-12.1/contrib/llvm/include/llvm/Analysis/
H A DVectorUtils.h258 : Align(Align), InsertPos(Instr) { in InterleaveGroup()
265 Members[0] = Instr; in InterleaveGroup()
303 Members[Key] = Instr; in insertMember()
321 unsigned getIndex(const InstTy *Instr) const { in getIndex() argument
323 if (I.second == Instr) in getIndex()
420 bool isInterleaved(Instruction *Instr) const { in isInterleaved() argument
429 if (InterleaveGroupMap.count(Instr)) in getInterleaveGroup()
430 return InterleaveGroupMap.find(Instr)->second; in getInterleaveGroup()
503 assert(!InterleaveGroupMap.count(Instr) && in createInterleaveGroup()
505 InterleaveGroupMap[Instr] = in createInterleaveGroup()
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/freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/
H A DR600OptimizeVectorRegisters.cpp77 MachineInstr *Instr; member in __anon298be07c0111::RegSeqInfo
84 MachineOperand &MO = Instr->getOperand(i); in RegSeqInfo()
85 unsigned Chan = Instr->getOperand(i + 1).getImm(); in RegSeqInfo()
96 return RSI.Instr == Instr; in operator ==()
206 unsigned Reg = RSI->Instr->getOperand(0).getReg(); in RebuildVector()
207 MachineBasicBlock::iterator Pos = RSI->Instr; in RebuildVector()
247 RSI->Instr->eraseFromParent(); in RebuildVector()
250 RSI->Instr = NewMI; in RebuildVector()
336 PreviousRegSeq[RSI.Instr] = RSI; in trackRSI()
386 RemoveMI(CandidateRSI.Instr); in runOnMachineFunction()
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/freebsd-12.1/contrib/llvm/lib/Target/Lanai/Disassembler/
H A DLanaiDisassembler.cpp89 static void PostOperandDecodeAdjust(MCInst &Instr, uint32_t Insn) { in PostOperandDecodeAdjust() argument
93 if (isRMOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
95 else if (isSPLSOpcode(Instr.getOpcode())) in PostOperandDecodeAdjust()
97 else if (isRRMOpcode(Instr.getOpcode())) { in PostOperandDecodeAdjust()
111 if (Instr.getOperand(2).isReg()) { in PostOperandDecodeAdjust()
112 Instr.getOperand(2).setReg(Lanai::R0); in PostOperandDecodeAdjust()
114 if (Instr.getOperand(2).isImm()) in PostOperandDecodeAdjust()
115 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
126 Instr.addOperand(MCOperand::createImm(AluOp)); in PostOperandDecodeAdjust()
131 MCInst &Instr, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t Address, in getInstruction() argument
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/freebsd-12.1/contrib/llvm/lib/Target/BPF/Disassembler/
H A DBPFDisassembler.cpp68 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
162 DecodeStatus BPFDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
179 Result = decodeInstruction(DecoderTableBPFALU3264, Instr, Insn, Address, in getInstruction()
182 Result = decodeInstruction(DecoderTableBPF64, Instr, Insn, Address, this, in getInstruction()
187 switch (Instr.getOpcode()) { in getInstruction()
199 auto& Op = Instr.getOperand(1); in getInstruction()
209 auto Op = Instr.getOperand(0); in getInstruction()
210 Instr.clear(); in getInstruction()
211 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
212 Instr.addOperand(Op); in getInstruction()
/freebsd-12.1/contrib/llvm/lib/Transforms/Scalar/
H A DCallSiteSplitting.cpp189 Instruction *Instr = CS.getInstruction(); in canSplitCallSite() local
190 if (!isa<CallInst>(Instr)) in canSplitCallSite()
193 BasicBlock *CallSiteBB = Instr->getParent(); in canSplitCallSite()
306 Instruction *Instr = CS.getInstruction(); in splitCallSite() local
307 BasicBlock *TailBB = Instr->getParent(); in splitCallSite()
317 CallPN->setDebugLoc(Instr->getDebugLoc()); in splitCallSite()
382 Instr->replaceAllUsesWith(CallPN); in splitCallSite()
392 auto I = Instr->getReverseIterator(); in splitCallSite()
418 Instruction *Instr = CS.getInstruction(); in isPredicatedOnPHI() local
419 BasicBlock *Parent = Instr->getParent(); in isPredicatedOnPHI()
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H A DCorrelatedValuePropagation.cpp507 assert(Instr->getOpcode() == Instruction::UDiv || in processUDivOrURem()
508 Instr->getOpcode() == Instruction::URem); in processUDivOrURem()
509 if (Instr->getType()->isVectorTy()) in processUDivOrURem()
514 auto OrigWidth = Instr->getType()->getIntegerBitWidth(); in processUDivOrURem()
516 for (Value *Operand : Instr->operands()) { in processUDivOrURem()
529 IRBuilder<> B{Instr}; in processUDivOrURem()
535 auto *BO = B.CreateBinOp(Instr->getOpcode(), LHS, RHS, Instr->getName()); in processUDivOrURem()
536 auto *Zext = B.CreateZExt(BO, Instr->getType(), Instr->getName() + ".zext"); in processUDivOrURem()
539 BinOp->setIsExact(Instr->isExact()); in processUDivOrURem()
541 Instr->replaceAllUsesWith(Zext); in processUDivOrURem()
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/freebsd-12.1/contrib/llvm/lib/Target/AArch64/
H A DAArch64PromoteConstant.cpp266 if (isa<const ExtractValueInst>(Instr) && OpIdx > 0) in shouldConvertUse()
270 if (isa<const InsertValueInst>(Instr) && OpIdx > 1) in shouldConvertUse()
273 if (isa<const AllocaInst>(Instr) && OpIdx > 0) in shouldConvertUse()
277 if (isa<const LoadInst>(Instr) && OpIdx > 0) in shouldConvertUse()
281 if (isa<const StoreInst>(Instr) && OpIdx > 1) in shouldConvertUse()
285 if (isa<const GetElementPtrInst>(Instr) && OpIdx > 0) in shouldConvertUse()
290 if (isa<const LandingPadInst>(Instr)) in shouldConvertUse()
294 if (isa<const SwitchInst>(Instr)) in shouldConvertUse()
298 if (isa<const IndirectBrInst>(Instr)) in shouldConvertUse()
302 if (isa<const IntrinsicInst>(Instr)) in shouldConvertUse()
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/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegBankSelect.h207 MachineInstr &Instr;
216 return Instr; in getPointImpl()
217 return Instr.getNextNode() ? *Instr.getNextNode() in getPointImpl()
218 : Instr.getParent()->end(); in getPointImpl()
222 return *Instr.getParent(); in getInsertMBBImpl()
227 InstrInsertPoint(MachineInstr &Instr, bool Before = true);
/freebsd-12.1/contrib/llvm/lib/Target/AVR/Disassembler/
H A DAVRDisassembler.cpp41 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
114 DecodeStatus AVRDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
130 Result = decodeInstruction(getDecoderTable(Size), Instr, in getInstruction()
143 Result = decodeInstruction(getDecoderTable(Size), Instr, Insn, in getInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/NVPTX/
H A DNVPTXImageOptimizer.cpp64 Instruction &Instr = *I; in runOnFunction() local
72 Changed |= replaceIsTypePSampler(Instr); in runOnFunction()
75 Changed |= replaceIsTypePSurface(Instr); in runOnFunction()
78 Changed |= replaceIsTypePTexture(Instr); in runOnFunction()
H A DNVPTXProxyRegErasure.cpp57 void replaceRegisterUsage(MachineInstr &Instr, MachineOperand &From,
110 void NVPTXProxyRegErasure::replaceRegisterUsage(MachineInstr &Instr, in replaceRegisterUsage() argument
113 for (auto &Op : Instr.uses()) { in replaceRegisterUsage()
/freebsd-12.1/contrib/llvm/tools/lld/ELF/Arch/
H A DPPC64.cpp189 static void writeInstrFromHalf16(uint8_t *Loc, uint32_t Instr) { in writeInstrFromHalf16() argument
190 write32(Loc - (Config->EKind == ELF64BEKind ? 2 : 0), Instr); in writeInstrFromHalf16()
682 uint32_t Instr = readInstrFromHalf16(Loc); in relocateOne() local
683 if (isInstructionUpdateForm(Instr)) in relocateOne()
686 utohexstr(Instr)); in relocateOne()
687 Instr = (Instr & 0xFFE00000) | 0x00020000; in relocateOne()
688 writeInstrFromHalf16(Loc, Instr); in relocateOne()
903 auto CheckRegOperands = [](uint32_t Instr, uint8_t ExpectedRT, in adjustPrologueForCrossSplitStack()
905 return ((Instr & 0x3E00000) >> 21 == ExpectedRT) && in adjustPrologueForCrossSplitStack()
906 ((Instr & 0x1F0000) >> 16 == ExpectedRA); in adjustPrologueForCrossSplitStack()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCLoopPreIncPrep.cpp128 BucketElement(const SCEVConstant *O, Instruction *I) : Offset(O), Instr(I) {} in BucketElement()
129 BucketElement(Instruction *I) : Offset(nullptr), Instr(I) {} in BucketElement()
132 Instruction *Instr; member
365 if (auto *II = dyn_cast<IntrinsicInst>(Buckets[i].Elements[j].Instr)) in runOnLoop()
403 Instruction *MemI = Buckets[i].Elements.begin()->Instr; in runOnLoop()
478 Value *Ptr = GetPointerOperand(I->Instr); in runOnLoop()
494 PtrIP = I->Instr; in runOnLoop()
498 I->Instr->hasName() ? I->Instr->getName() + ".off" : "", PtrIP); in runOnLoop()
/freebsd-12.1/contrib/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugFrame.cpp219 bool IsEH, const Instruction &Instr, in printOperand() argument
222 uint8_t Opcode = Instr.Opcode; in printOperand()
268 assert(Instr.Expression && "missing DWARFExpression object"); in printOperand()
270 Instr.Expression->print(OS, MRI, IsEH); in printOperand()
277 for (const auto &Instr : Instructions) { in dump() local
278 uint8_t Opcode = Instr.Opcode; in dump()
283 for (unsigned i = 0; i < Instr.Ops.size(); ++i) in dump()
284 printOperand(OS, MRI, IsEH, Instr, i, Instr.Ops[i]); in dump()
/freebsd-12.1/contrib/llvm/lib/Target/XCore/
H A DXCoreLowerThreadLocal.cpp78 createReplacementInstr(ConstantExpr *CE, Instruction *Instr) { in createReplacementInstr() argument
79 IRBuilder<NoFolder> Builder(Instr); in createReplacementInstr()
146 } else if (Instruction *Instr = dyn_cast<Instruction>(WU)) { in replaceConstantExprOp() local
147 Instruction *NewInst = createReplacementInstr(CE, Instr); in replaceConstantExprOp()
148 Instr->replaceUsesOfWith(CE, NewInst); in replaceConstantExprOp()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCDwarf.cpp1318 switch (Instr.getOperation()) { in EmitCFIInstruction()
1340 unsigned Reg = Instr.getRegister(); in EmitCFIInstruction()
1353 CFAOffset += Instr.getOffset(); in EmitCFIInstruction()
1355 CFAOffset = -Instr.getOffset(); in EmitCFIInstruction()
1362 unsigned Reg = Instr.getRegister(); in EmitCFIInstruction()
1367 CFAOffset = -Instr.getOffset(); in EmitCFIInstruction()
1373 unsigned Reg = Instr.getRegister(); in EmitCFIInstruction()
1386 unsigned Reg = Instr.getRegister(); in EmitCFIInstruction()
1390 int Offset = Instr.getOffset(); in EmitCFIInstruction()
1416 unsigned Reg = Instr.getRegister(); in EmitCFIInstruction()
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/freebsd-12.1/contrib/llvm/lib/CodeGen/GlobalISel/
H A DRegBankSelect.cpp772 RegBankSelect::InstrInsertPoint::InstrInsertPoint(MachineInstr &Instr, in InstrInsertPoint() argument
774 : InsertPoint(), Instr(Instr), Before(Before) { in InstrInsertPoint()
777 assert((!Before || !Instr.isPHI()) && in InstrInsertPoint()
779 assert((!Before || !Instr.getNextNode() || !Instr.getNextNode()->isPHI()) && in InstrInsertPoint()
808 return Instr.isTerminator(); in isSplit()
811 return Instr.getPrevNode() && Instr.getPrevNode()->isTerminator(); in isSplit()
821 return MBFI->getBlockFreq(Instr.getParent()).getFrequency(); in frequency()
/freebsd-12.1/contrib/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp1497 (!Instr || in getBroadcastInstrs()
2001 if (Instr != Group->getInsertPos()) in vectorizeInterleaveGroup()
2062 setDebugLocFromInst(Builder, Instr); in vectorizeInterleaveGroup()
2072 if (isa<LoadInst>(Instr)) { in vectorizeInterleaveGroup()
2339 addNewMetadata(Cloned, Instr); in scalarizeInstruction()
5108 if (!Instr) in calculateRegisterUsage()
5119 Ends.insert(Instr); in calculateRegisterUsage()
6668 Instr->getType()->isVoidTy() ? nullptr : new VPPredInstPHIRecipe(Instr); in createReplicateRegion()
6799 Instruction *Instr = &I; in buildVPlanWithVPRecipes() local
6803 if (isa<BranchInst>(Instr) || in buildVPlanWithVPRecipes()
[all …]
H A DLoopVectorizationPlanner.h43 VPInstruction *Instr = new VPInstruction(Opcode, Operands); in createInstruction() local
45 BB->insert(Instr, InsertPt); in createInstruction()
46 return Instr; in createInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/ARC/Disassembler/
H A DARCDisassembler.cpp43 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
297 DecodeStatus ARCDisassembler::getInstruction(MCInst &Instr, uint64_t &Size, in getInstruction() argument
323 decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI); in getInstruction()
335 return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI); in getInstruction()
343 decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI); in getInstruction()
358 return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI); in getInstruction()
/freebsd-12.1/contrib/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp22 MachineInstr *Instr) { in WebAssemblyDebugValueManager() argument
23 Instr->collectDebugValues(DbgValues); in WebAssemblyDebugValueManager()
/freebsd-12.1/contrib/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h251 MachineInstr *Instr = nullptr; ///< Alternatively, a MachineInstr.
324 : Instr(instr), NodeNum(nodenum), isVRegCycle(false), isCall(false),
353 assert(!Instr && "Setting SDNode of SUnit with MachineInstr!");
360 assert(!Instr && "Reading SDNode of SUnit with MachineInstr!");
366 bool isInstr() const { return Instr; }
372 Instr = MI;
379 return Instr;
H A DLiveIntervals.h221 bool isNotInMIMap(const MachineInstr &Instr) const { in isNotInMIMap() argument
222 return !Indexes->hasIndex(Instr); in isNotInMIMap()
226 SlotIndex getInstructionIndex(const MachineInstr &Instr) const { in getInstructionIndex() argument
227 return Indexes->getInstructionIndex(Instr); in getInstructionIndex()

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