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Searched refs:ImplicitDefs (Results 1 – 19 of 19) sorted by relevance

/freebsd-12.1/contrib/llvm/include/llvm/MC/
H A DMCInstrDesc.h174 const MCPhysReg *ImplicitDefs; // Registers implicitly defined by this instr variable
546 const MCPhysReg *getImplicitDefs() const { return ImplicitDefs; } in getImplicitDefs()
550 if (!ImplicitDefs) in getNumImplicitDefs()
553 for (; ImplicitDefs[i]; ++i) /*empty*/ in getNumImplicitDefs()
/freebsd-12.1/contrib/llvm/lib/CodeGen/
H A DMachineCSE.cpp495 SmallVector<unsigned, 2> ImplicitDefs; in ProcessBlock() local
589 ImplicitDefs.push_back(OldReg); in ProcessBlock()
651 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
658 for (auto ImplicitDef : ImplicitDefs) in ProcessBlock()
686 ImplicitDefs.clear(); in ProcessBlock()
H A DMachineInstr.cpp103 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
/freebsd-12.1/contrib/llvm/utils/TableGen/
H A DInstrDocsEmitter.cpp193 if (!II->ImplicitDefs.empty()) { in EmitInstrDocs()
196 for (Record *Def : II->ImplicitDefs) { in EmitInstrDocs()
H A DCodeGenInstruction.cpp388 ImplicitDefs = R->getValueAsListOfDefs("Defs"); in CodeGenInstruction()
421 if (ImplicitDefs.empty()) return MVT::Other; in HasOneImplicitDefWithKnownVT()
424 Record *FirstImplicitDef = ImplicitDefs[0]; in HasOneImplicitDefWithKnownVT()
H A DCodeGenInstruction.h232 std::vector<Record*> ImplicitDefs, ImplicitUses; variable
H A DDAGISelMatcherGen.cpp851 HandledReg = II.ImplicitDefs[0]; in EmitResultInstructionAsOperand()
993 HandledReg = II.ImplicitDefs[0]; in EmitResultCode()
H A DGlobalISelEmitter.cpp2572 if (!I->ImplicitDefs.empty() || !I->ImplicitUses.empty()) { in emitActionOpcodes()
2573 for (auto Def : I->ImplicitDefs) { in emitActionOpcodes()
3035 const std::vector<Record *> &ImplicitDefs) const;
3822 const std::vector<Record *> &ImplicitDefs) const { in importImplicitDefRenderers()
3823 if (!ImplicitDefs.empty()) in importImplicitDefRenderers()
H A DCodeGenDAGPatterns.cpp2380 if (!InstInfo.ImplicitDefs.empty()) { in ApplyTypeConstraints()
/freebsd-12.1/contrib/llvm/lib/MC/
H A DMCInstrDesc.cpp47 if (const MCPhysReg *ImpDefs = ImplicitDefs) in hasImplicitDefOfPhysReg()
/freebsd-12.1/contrib/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp2055 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_r()
2080 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rr()
2108 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrr()
2130 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_ri()
2155 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rii()
2174 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_f()
2200 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rri()
2216 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_i()
H A DScheduleDAGFast.cpp434 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
512 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
H A DScheduleDAGSDNodes.cpp129 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) in CheckForPhysRegDependency()
H A DScheduleDAGRRList.cpp1273 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1413 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
/freebsd-12.1/contrib/llvm/lib/Target/Hexagon/
H A DHexagonGenMux.cpp164 if (const MCPhysReg *R = D.ImplicitDefs) in getDefsUses()
/freebsd-12.1/contrib/llvm/lib/Target/ARM/
H A DARMFastISel.cpp321 .addReg(II.ImplicitDefs[0])); in fastEmitInst_r()
349 .addReg(II.ImplicitDefs[0])); in fastEmitInst_rr()
375 .addReg(II.ImplicitDefs[0])); in fastEmitInst_ri()
394 .addReg(II.ImplicitDefs[0])); in fastEmitInst_i()
/freebsd-12.1/contrib/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp946 if (MCID.ImplicitDefs) in verifyImplicitOperands()
/freebsd-12.1/contrib/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1961 if (NewDesc.ImplicitDefs) in optimizeCompareInstr()
/freebsd-12.1/contrib/llvm/lib/Target/X86/
H A DX86FastISel.cpp4027 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); in fastEmitInst_rrrr()