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Searched refs:INTEL_INFO (Results 1 – 23 of 23) sorted by relevance

/freebsd-12.1/sys/dev/drm2/i915/
H A Di915_drv.h1158 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1160 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1167 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1171 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1193 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1194 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1195 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1196 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1197 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1198 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
[all …]
H A Dintel_panel.c127 if (INTEL_INFO(dev)->gen >= 4) in is_backlight_combination_mode()
155 if (INTEL_INFO(dev)->gen >= 4) in i915_read_blc_pwm_ctl()
161 if (INTEL_INFO(dev)->gen >= 4) in i915_read_blc_pwm_ctl()
179 if (INTEL_INFO(dev)->gen < 4) in _intel_panel_get_max_backlight()
239 if (INTEL_INFO(dev)->gen < 4) in intel_panel_get_backlight()
283 if (INTEL_INFO(dev)->gen < 4) in intel_panel_actually_set_backlight()
305 if (INTEL_INFO(dev)->gen >= 4) { in intel_panel_disable_backlight()
328 if (INTEL_INFO(dev)->gen >= 4) { in intel_panel_enable_backlight()
H A Di915_gem_tiling.c100 } else if (INTEL_INFO(dev)->gen >= 6) { in i915_gem_detect_bit_6_swizzle()
223 if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
242 if (INTEL_INFO(dev)->gen >= 4) { in i915_tiling_ok()
267 if (INTEL_INFO(obj->base.dev)->gen >= 4) in i915_gem_object_fence_ok()
270 if (INTEL_INFO(obj->base.dev)->gen == 3) { in i915_gem_object_fence_ok()
282 if (INTEL_INFO(obj->base.dev)->gen == 3) in i915_gem_object_fence_ok()
H A Di915_gem_gtt.c331 if (INTEL_INFO(dev)->gen == 6) { in i915_gem_init_ppgtt()
344 } else if (INTEL_INFO(dev)->gen >= 7) { in i915_gem_init_ppgtt()
350 if (INTEL_INFO(dev)->gen >= 7) in i915_gem_init_ppgtt()
392 if (INTEL_INFO(dev)->gen < 6) { in i915_ggtt_clear_range()
488 if (INTEL_INFO(dev)->gen < 6) { in i915_gem_gtt_bind_object()
657 if (INTEL_INFO(dev)->gen < 6) { in i915_gem_gtt_init()
698 if (INTEL_INFO(dev)->gen < 7) in i915_gem_gtt_init()
742 if (INTEL_INFO(dev)->gen < 6) in i915_gem_gtt_init()
755 if (INTEL_INFO(dev)->gen < 6) in i915_gem_gtt_fini()
758 if (INTEL_INFO(dev)->gen >= 6) in i915_gem_gtt_fini()
H A Dintel_ringbuffer.c516 if (INTEL_INFO(dev)->gen > 3) in init_render_ring()
523 if (INTEL_INFO(dev)->gen >= 6) in init_render_ring()
527 if (INTEL_INFO(dev)->gen == 6) in init_render_ring()
536 if (INTEL_INFO(dev)->gen >= 5) { in init_render_ring()
559 if (INTEL_INFO(dev)->gen >= 6) in init_render_ring()
1610 if (INTEL_INFO(dev)->gen >= 6) { in intel_init_render_ring_buffer()
1613 if (INTEL_INFO(dev)->gen == 6) in intel_init_render_ring_buffer()
1634 if (INTEL_INFO(dev)->gen < 4) in intel_init_render_ring_buffer()
1696 if (INTEL_INFO(dev)->gen >= 6) { in intel_render_ring_init_dri()
1705 if (INTEL_INFO(dev)->gen < 4) in intel_render_ring_init_dri()
[all …]
H A Di915_suspend.c276 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_save_modeset_reg()
314 if (INTEL_INFO(dev)->gen >= 4) { in i915_save_modeset_reg()
333 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) in i915_save_modeset_reg()
371 if (INTEL_INFO(dev)->gen >= 4) { in i915_save_modeset_reg()
379 switch (INTEL_INFO(dev)->gen) { in i915_save_modeset_reg()
420 switch (INTEL_INFO(dev)->gen) { in i915_restore_modeset_reg()
477 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) { in i915_restore_modeset_reg()
521 if (INTEL_INFO(dev)->gen >= 4) { in i915_restore_modeset_reg()
590 if (INTEL_INFO(dev)->gen >= 4) { in i915_restore_modeset_reg()
645 if (INTEL_INFO(dev)->gen >= 4) in i915_save_display()
[all …]
H A Di915_gem_stolen.c66 if (INTEL_INFO(dev)->gen >= 6) { in i915_stolen_to_physical()
73 } else if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) { in i915_stolen_to_physical()
H A Di915_irq.c107 if (INTEL_INFO(dev)->gen >= 4) in intel_enable_asle()
203 if (INTEL_INFO(dev)->gen >= 4) { in i915_get_crtc_scanoutpos()
866 switch(INTEL_INFO(dev)->gen) { in i915_get_extra_instdone()
1058 switch (INTEL_INFO(dev)->gen) { in i915_gem_record_fences()
1129 if (INTEL_INFO(dev)->gen >= 6) { in i915_record_ring_state()
1140 if (INTEL_INFO(dev)->gen >= 4) { in i915_record_ring_state()
1257 if (INTEL_INFO(dev)->gen >= 6) in i915_capture_error_state()
1270 if (INTEL_INFO(dev)->gen >= 6) { in i915_capture_error_state()
1275 if (INTEL_INFO(dev)->gen == 7) in i915_capture_error_state()
1409 if (INTEL_INFO(dev)->gen < 4) { in i915_report_and_clear_eir()
[all …]
H A Di915_gem_context.c111 switch (INTEL_INFO(dev)->gen) { in get_context_size()
125 INTEL_INFO(dev)->gen); in get_context_size()
168 if (INTEL_INFO(dev)->gen >= 7) { in create_hw_context()
H A Di915_gem_execbuffer.c350 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; in i915_gem_execbuffer_reserve_object()
417 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4; in i915_gem_execbuffer_reserve()
921 if (INTEL_INFO(dev)->gen < 4) { in i915_gem_do_execbuffer()
926 if (INTEL_INFO(dev)->gen > 5 && in i915_gem_do_execbuffer()
933 if (INTEL_INFO(dev)->gen >= 6) in i915_gem_do_execbuffer()
956 if (INTEL_INFO(dev)->gen >= 5) { in i915_gem_do_execbuffer()
1201 if (INTEL_INFO(dev)->gen < 4) in i915_gem_execbuffer()
H A Dintel_lvds.c262 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { in intel_lvds_mode_fixup()
292 if (INTEL_INFO(dev)->gen >= 4) in intel_lvds_mode_fixup()
320 if (INTEL_INFO(dev)->gen >= 4) { in intel_lvds_mode_fixup()
380 if (INTEL_INFO(dev)->gen >= 4) in intel_lvds_mode_fixup()
402 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) in intel_lvds_mode_fixup()
H A Di915_dma.c95 if (INTEL_INFO(dev)->gen >= 4) in i915_write_hws_pga()
388 if (INTEL_INFO(dev)->gen >= 4) { in i915_emit_box()
501 if (INTEL_INFO(dev)->gen >= 4) { in i915_dispatch_batchbuffer()
967 value = INTEL_INFO(dev)->gen >= 4; in i915_getparam()
1120 int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_alloc_mchbar_resource()
1124 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
1148 if (INTEL_INFO(dev)->gen >= 4) in intel_alloc_mchbar_resource()
1162 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_setup_mchbar()
1199 int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915; in intel_teardown_mchbar()
H A Di915_debug.c58 const struct intel_device_info *info = INTEL_INFO(dev); in i915_capabilities()
624 if (ring == RCS && INTEL_INFO(dev)->gen >= 4) in i915_ring_error_state()
627 if (INTEL_INFO(dev)->gen >= 4) in i915_ring_error_state()
631 if (INTEL_INFO(dev)->gen >= 6) { in i915_ring_error_state()
684 if (INTEL_INFO(dev)->gen >= 6) { in i915_error_state()
689 if (INTEL_INFO(dev)->gen == 7) in i915_error_state()
1395 if (INTEL_INFO(dev)->gen == 6) in i915_ppgtt_info()
1400 if (INTEL_INFO(dev)->gen == 7) in i915_ppgtt_info()
H A Di915_drv.c480 if (INTEL_INFO(dev)->gen < 6) in i915_semaphore_is_enabled()
488 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) in i915_semaphore_is_enabled()
813 switch (INTEL_INFO(dev)->gen) { in intel_gpu_reset()
1430 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) in i915_reg_read_ioctl()
H A Di915_gem.c207 if (INTEL_INFO(dev)->gen >= 5) in i915_gem_init_ioctl()
1676 if (INTEL_INFO(dev)->gen >= 4 || in i915_gem_get_gtt_size()
1681 if (INTEL_INFO(dev)->gen == 3) in i915_gem_get_gtt_size()
1708 if (INTEL_INFO(dev)->gen >= 4 || in i915_gem_get_gtt_alignment()
1737 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || in i915_gem_get_unfenced_gtt_alignment()
2922 switch (INTEL_INFO(dev)->gen) { in i915_gem_write_fence()
3454 if (INTEL_INFO(dev)->gen < 6) { in i915_gem_object_set_cache_level()
4200 if (INTEL_INFO(dev)->gen < 5 || in i915_gem_init_swizzling()
4240 if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) in i915_gem_init_hw()
4293 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) in intel_enable_ppgtt()
[all …]
H A Dintel_sprite.c678 if (INTEL_INFO(dev)->gen < 5) in intel_plane_init()
685 switch (INTEL_INFO(dev)->gen) { in intel_plane_init()
H A Dintel_display.c963 if (INTEL_INFO(dev)->gen >= 5) { in intel_wait_for_vblank()
1014 if (INTEL_INFO(dev)->gen >= 4) { in intel_wait_for_pipe_off()
2096 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_plane()
2107 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_plane()
2120 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_plane()
4342 if (INTEL_INFO(dev)->gen >= 4) { in intel_update_lvds()
4513 if (INTEL_INFO(dev)->gen >= 4) in i9xx_update_pll()
4549 if (INTEL_INFO(dev)->gen >= 4) { in i9xx_update_pll()
4651 if (INTEL_INFO(dev)->gen > 3) in intel_set_pipe_timings()
7442 if (INTEL_INFO(dev)->gen > 3 && in intel_crtc_page_flip()
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H A Dintel_sdvo.c1149 if (INTEL_INFO(dev)->gen >= 4) { in intel_sdvo_mode_set()
1155 if (INTEL_INFO(dev)->gen < 5) in intel_sdvo_mode_set()
1178 if (INTEL_INFO(dev)->gen >= 4) { in intel_sdvo_mode_set()
1187 INTEL_INFO(dev)->gen < 5) in intel_sdvo_mode_set()
2206 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) in intel_sdvo_add_hdmi_properties()
H A Dintel_pm.c446 if (INTEL_INFO(dev)->gen <= 6) in intel_update_fbc()
2508 if (INTEL_INFO(dev)->gen == 5) in intel_enable_rc6()
2517 if (INTEL_INFO(dev)->gen == 6) { in intel_enable_rc6()
3454 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) { in intel_disable_gt_powersave()
4435 } else if (INTEL_INFO(dev)->gen >= 6) { in intel_gt_reset()
H A Dintel_overlay.c838 if (INTEL_INFO(overlay->dev)->gen < 4 && in check_overlay_possible_on_crtc()
855 if (INTEL_INFO(dev)->gen >= 4) { in update_pfit_vscale_ratio()
H A Dintel_bios.c331 switch (INTEL_INFO(dev)->gen) { in intel_bios_ssc_frequency()
H A Dintel_crt.c139 if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) in intel_crt_dpms()
H A Dintel_tv.c1080 if (INTEL_INFO(dev)->gen >= 4) in intel_tv_mode_set()