| /freebsd-12.1/contrib/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 811 unsigned HiReg = HiOperand.getReg(); in emitCombineRI() local
819 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
827 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
851 .addReg(HiReg, HiRegKillFlag) in emitCombineRI()
862 unsigned HiReg = HiOperand.getReg(); in emitCombineRR() local
879 .addReg(HiReg, HiRegKillFlag) in emitCombineRR()
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| H A D | HexagonPatterns.td | 797 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
807 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
825 (Combinew (C2_mux I1:$Pu, (HiReg $Rs), (HiReg $Rt)),
1383 (Combinew (M2_mpyu_up (HiReg $Rss), (HiReg $Rtt)),
1387 (Combinew (M2_mpy_up (HiReg $Rs), (HiReg $Rt)),
1392 (Combinew (S2_vtrunohb (M5_vmpybuu (HiReg $Rss), (HiReg $Rtt))),
1411 OutPatFrag<(ops node:$Rss, node:$Rtt), (Mpysh (HiReg $Rss), (HiReg $Rtt))>;
1550 (HiReg $Rss),
1551 (HiReg $Rtt)),
1626 (S2_vtrunewh (M2_vmpy2s_s0 (HiReg $Rs), (HiReg $Rt)),
[all …]
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| H A D | HexagonIntrinsics.td | 96 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
98 (A2_combinew (HiReg I64:$Rs), (LoReg I64:$Rs))>;
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| H A D | HexagonFrameLowering.cpp | 977 unsigned HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi); in insertCFIInstructionsAt() local
979 unsigned HiDwarfReg = HRI.getDwarfRegNum(HiReg, true); in insertCFIInstructionsAt()
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| /freebsd-12.1/contrib/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.h | 53 void splitReg(unsigned Reg, unsigned &LoReg, unsigned &HiReg) const;
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| H A D | AVRRegisterInfo.cpp | 269 unsigned &HiReg) const { in splitReg()
273 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| /freebsd-12.1/contrib/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 141 unsigned HiReg = 0; member
1132 assert((TRI->getRegSizeInBits(Addr.Base.HiReg, *MRI) == 32 || in computeBase()
1157 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg) in computeBase()
1257 Addr.Base.HiReg = BaseHi.getReg(); in processBaseWithConstOffset()
1302 LLVM_DEBUG(dbgs() << " BASE: {" << MAddr.Base.HiReg << ", " in promoteConstantOffsetToImm()
1360 MAddrNext.Base.HiReg != MAddr.Base.HiReg || in promoteConstantOffsetToImm()
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| H A D | AMDGPUInstructionSelector.cpp | 362 unsigned HiReg = MRI.createVirtualRegister(RC); in selectG_CONSTANT() local
368 BuildMI(*BB, &I, DL, TII.get(Opcode), HiReg) in selectG_CONSTANT()
375 .addReg(HiReg) in selectG_CONSTANT()
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| /freebsd-12.1/contrib/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 3612 unsigned SrcReg, LoReg, HiReg; in Select() local
3617 SrcReg = LoReg = X86::EAX; HiReg = X86::EDX; in Select()
3621 SrcReg = LoReg = X86::RAX; HiReg = X86::RDX; in Select()
3669 assert(HiReg && "Register for high half is not defined!"); in Select()
3707 unsigned LoReg, HiReg, ClrReg; in Select() local
3712 LoReg = X86::AL; ClrReg = HiReg = X86::AH; in Select()
3716 LoReg = X86::AX; HiReg = X86::DX; in Select()
3721 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; in Select()
3725 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; in Select()
3817 if (HiReg == X86::AH && !SDValue(Node, 1).use_empty()) { in Select()
[all …]
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| /freebsd-12.1/contrib/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 310 unsigned HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
326 std::swap(LoReg, HiReg); in expandBuildPairF64()
329 TII.storeRegToStack(MBB, I, HiReg, I->getOperand(2).isKill(), FI, RC, in expandBuildPairF64()
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| H A D | MipsSEInstrInfo.cpp | 820 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); in expandBuildPairF64() local
868 .addReg(HiReg); in expandBuildPairF64()
873 .addReg(HiReg); in expandBuildPairF64()
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| /freebsd-12.1/contrib/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 603 unsigned HiReg = MI.getOperand(1).getReg(); in emitSplitF64Pseudo() local
617 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg) in emitSplitF64Pseudo()
636 unsigned HiReg = MI.getOperand(2).getReg(); in emitBuildPairF64Pseudo() local
649 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill())) in emitBuildPairF64Pseudo()
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| /freebsd-12.1/contrib/llvm/lib/Target/ARM/AsmParser/ |
| H A D | ARMAsmParser.cpp | 6313 unsigned Reg, unsigned HiReg, in checkLowRegisterList() argument
6321 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg)) in checkLowRegisterList()
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| /freebsd-12.1/contrib/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 10516 unsigned HiReg = MI.getOperand(1).getReg(); in EmitInstrWithCustomInserter() local
10518 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269); in EmitInstrWithCustomInserter()
10525 .addReg(HiReg) in EmitInstrWithCustomInserter()
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